提交 4a09d0bb 编写于 作者: R Richard Henderson

target/openrisc: Rename the cpu from or32 to or1k

This is in keeping with the toolchain and or1ksim.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
上级 305e6c8a
......@@ -5843,7 +5843,7 @@ target_name=$(echo $target | cut -d '-' -f 1)
target_bigendian="no"
case "$target_name" in
armeb|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
armeb|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
target_bigendian=yes
;;
esac
......@@ -5937,7 +5937,7 @@ case "$target_name" in
;;
nios2)
;;
or32)
or1k)
TARGET_ARCH=openrisc
TARGET_BASE_ARCH=openrisc
;;
......@@ -6145,7 +6145,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
nios2)
disas_config "NIOS2"
;;
or32)
or1k)
disas_config "OPENRISC"
;;
ppc*)
......
# Default configuration for or1k-linux-user
# Default configuration for or32-softmmu
# Default configuration for or1k-softmmu
CONFIG_SERIAL=y
CONFIG_OPENCORES_ETH=y
# Default configuration for or32-linux-user
......@@ -139,10 +139,10 @@ static void openrisc_sim_init(MachineState *machine)
static void openrisc_sim_machine_init(MachineClass *mc)
{
mc->desc = "or32 simulation";
mc->desc = "or1k simulation";
mc->init = openrisc_sim_init;
mc->max_cpus = 1;
mc->is_default = 1;
}
DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init)
DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
......@@ -32,7 +32,7 @@ struct OpenRISCCPU;
#include "fpu/softfloat.h"
#include "qom/cpu.h"
#define TYPE_OPENRISC_CPU "or32-cpu"
#define TYPE_OPENRISC_CPU "or1k-cpu"
#define OPENRISC_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
......
-include ../../config-host.mak
CROSS = or32-linux-
CROSS = or1k-linux-
SIM = qemu-or32
SIM = qemu-or1k
CC = $(CROSS)gcc
......
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