target/riscv: fix vector index load/store constraints
Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: NLIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
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