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3bbfbd1f
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体验新版 GitCode,发现更多精彩内容 >>
提交
3bbfbd1f
编写于
9月 01, 2012
作者:
R
Richard Henderson
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
target-s390: Convert AND, OR, XOR
Signed-off-by:
N
Richard Henderson
<
rth@twiddle.net
>
上级
1ac5889f
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
56 addition
and
105 deletion
+56
-105
target-s390x/insn-data.def
target-s390x/insn-data.def
+27
-0
target-s390x/translate.c
target-s390x/translate.c
+29
-105
未找到文件。
target-s390x/insn-data.def
浏览文件 @
3bbfbd1f
...
...
@@ -41,6 +41,24 @@
C(0xeb7e, ALGSI, SIY, GIE, m1_64, i2, new, m1_64, add, addu64)
C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64)
/* AND */
C(0x1400, NR, RR_a, Z, r1, r2, new, r1_32, and, nz32)
C(0xb9f4, NRK, RRF_a, DO, r2, r3, new, r1_32, and, nz32)
C(0x5400, N, RX_a, Z, r1, m2_32s, new, r1_32, and, nz32)
C(0xe354, NY, RXY_a, LD, r1, m2_32s, new, r1_32, and, nz32)
C(0xb980, NGR, RRE, Z, r1, r2, r1, 0, and, nz64)
C(0xb9e4, NGRK, RRF_a, DO, r2, r3, r1, 0, and, nz64)
C(0xe380, NG, RXY_a, Z, r1, m2_64, r1, 0, and, nz64)
/* EXCLUSIVE OR */
C(0x1700, XR, RR_a, Z, r1, r2, new, r1_32, xor, nz32)
C(0xb9f7, XRK, RRF_a, DO, r2, r3, new, r1_32, xor, nz32)
C(0x5700, X, RX_a, Z, r1, m2_32s, new, r1_32, xor, nz32)
C(0xe357, XY, RXY_a, LD, r1, m2_32s, new, r1_32, xor, nz32)
C(0xb982, XGR, RRE, Z, r1, r2, r1, 0, xor, nz64)
C(0xb9e7, XGRK, RRF_a, DO, r2, r3, r1, 0, xor, nz64)
C(0xe382, XG, RXY_a, Z, r1, m2_64, r1, 0, xor, nz64)
/* MULTIPLY */
C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0)
C(0x5c00, M, RX_a, Z, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
...
...
@@ -68,6 +86,15 @@
C(0xc201, MSFI, RIL_a, GIE, r1_o, i2, new, r1_32, mul, 0)
C(0xc200, MSGFI, RIL_a, GIE, r1_o, i2, r1, 0, mul, 0)
/* OR */
C(0x1600, OR, RR_a, Z, r1, r2, new, r1_32, or, nz32)
C(0xb9f6, ORK, RRF_a, DO, r2, r3, new, r1_32, or, nz32)
C(0x5600, O, RX_a, Z, r1, m2_32s, new, r1_32, or, nz32)
C(0xe356, OY, RXY_a, LD, r1, m2_32s, new, r1_32, or, nz32)
C(0xb981, OGR, RRE, Z, r1, r2, r1, 0, or, nz64)
C(0xb9e6, OGRK, RRF_a, DO, r2, r3, r1, 0, or, nz64)
C(0xe381, OG, RXY_a, Z, r1, m2_64, r1, 0, or, nz64)
/* SUBTRACT */
C(0x1b00, SR, RR_a, Z, r1, r2, new, r1_32, sub, subs32)
C(0xb9f9, SRK, RRF_a, DO, r2, r3, new, r1_32, sub, subs32)
...
...
target-s390x/translate.c
浏览文件 @
3bbfbd1f
...
...
@@ -1487,19 +1487,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
tcg_gen_qemu_st32
(
tmp2
,
addr
,
get_mem_index
(
s
));
tcg_temp_free_i64
(
tmp2
);
break
;
case
0x57
:
/* XY R1,D2(X2,B2) [RXY] */
tmp32_1
=
load_reg32
(
r1
);
tmp32_2
=
tcg_temp_new_i32
();
tmp2
=
tcg_temp_new_i64
();
tcg_gen_qemu_ld32u
(
tmp2
,
addr
,
get_mem_index
(
s
));
tcg_gen_trunc_i64_i32
(
tmp32_2
,
tmp2
);
tcg_temp_free_i64
(
tmp2
);
tcg_gen_xor_i32
(
tmp32_2
,
tmp32_1
,
tmp32_2
);
store_reg32
(
r1
,
tmp32_2
);
set_cc_nz_u32
(
s
,
tmp32_2
);
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_2
);
break
;
case
0x58
:
/* LY R1,D2(X2,B2) [RXY] */
tmp3
=
tcg_temp_new_i64
();
tcg_gen_qemu_ld32u
(
tmp3
,
addr
,
get_mem_index
(
s
));
...
...
@@ -1547,27 +1534,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
store_reg32_i64
(
r1
,
tmp2
);
tcg_temp_free_i64
(
tmp2
);
break
;
case
0x80
:
/* NG R1,D2(X2,B2) [RXY] */
case
0x81
:
/* OG R1,D2(X2,B2) [RXY] */
case
0x82
:
/* XG R1,D2(X2,B2) [RXY] */
tmp3
=
tcg_temp_new_i64
();
tcg_gen_qemu_ld64
(
tmp3
,
addr
,
get_mem_index
(
s
));
switch
(
op
)
{
case
0x80
:
tcg_gen_and_i64
(
regs
[
r1
],
regs
[
r1
],
tmp3
);
break
;
case
0x81
:
tcg_gen_or_i64
(
regs
[
r1
],
regs
[
r1
],
tmp3
);
break
;
case
0x82
:
tcg_gen_xor_i64
(
regs
[
r1
],
regs
[
r1
],
tmp3
);
break
;
default:
tcg_abort
();
}
set_cc_nz_u64
(
s
,
regs
[
r1
]);
tcg_temp_free_i64
(
tmp3
);
break
;
case
0x87
:
/* DLG R1,D2(X2,B2) [RXY] */
tmp2
=
tcg_temp_new_i64
();
tmp32_1
=
tcg_const_i32
(
r1
);
...
...
@@ -3115,29 +3081,6 @@ static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
store_reg32
(
r1
,
tmp32_1
);
tcg_temp_free_i32
(
tmp32_1
);
break
;
case
0x80
:
/* NGR R1,R2 [RRE] */
case
0x81
:
/* OGR R1,R2 [RRE] */
case
0x82
:
/* XGR R1,R2 [RRE] */
tmp
=
load_reg
(
r1
);
tmp2
=
load_reg
(
r2
);
switch
(
op
)
{
case
0x80
:
tcg_gen_and_i64
(
tmp
,
tmp
,
tmp2
);
break
;
case
0x81
:
tcg_gen_or_i64
(
tmp
,
tmp
,
tmp2
);
break
;
case
0x82
:
tcg_gen_xor_i64
(
tmp
,
tmp
,
tmp2
);
break
;
default:
tcg_abort
();
}
store_reg
(
r1
,
tmp
);
set_cc_nz_u64
(
s
,
tmp
);
tcg_temp_free_i64
(
tmp
);
tcg_temp_free_i64
(
tmp2
);
break
;
case
0x83
:
/* FLOGR R1,R2 [RRE] */
tmp
=
load_reg
(
r2
);
tmp32_1
=
tcg_const_i32
(
r1
);
...
...
@@ -3392,23 +3335,6 @@ static void disas_c2(CPUS390XState *env, DisasContext *s, int op, int r1,
}
}
static
void
gen_and_or_xor_i32
(
int
opc
,
TCGv_i32
tmp
,
TCGv_i32
tmp2
)
{
switch
(
opc
&
0xf
)
{
case
0x4
:
tcg_gen_and_i32
(
tmp
,
tmp
,
tmp2
);
break
;
case
0x6
:
tcg_gen_or_i32
(
tmp
,
tmp
,
tmp2
);
break
;
case
0x7
:
tcg_gen_xor_i32
(
tmp
,
tmp
,
tmp2
);
break
;
default:
tcg_abort
();
}
}
static
void
disas_s390_insn
(
CPUS390XState
*
env
,
DisasContext
*
s
)
{
TCGv_i64
tmp
,
tmp2
,
tmp3
,
tmp4
;
...
...
@@ -3543,19 +3469,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
set_cc_comp32
(
s
,
tmp32_1
);
tcg_temp_free_i32
(
tmp32_1
);
break
;
case
0x14
:
/* NR R1,R2 [RR] */
case
0x16
:
/* OR R1,R2 [RR] */
case
0x17
:
/* XR R1,R2 [RR] */
insn
=
ld_code2
(
env
,
s
->
pc
);
decode_rr
(
s
,
insn
,
&
r1
,
&
r2
);
tmp32_2
=
load_reg32
(
r2
);
tmp32_1
=
load_reg32
(
r1
);
gen_and_or_xor_i32
(
opc
,
tmp32_1
,
tmp32_2
);
store_reg32
(
r1
,
tmp32_1
);
set_cc_nz_u32
(
s
,
tmp32_1
);
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_2
);
break
;
case
0x18
:
/* LR R1,R2 [RR] */
insn
=
ld_code2
(
env
,
s
->
pc
);
decode_rr
(
s
,
insn
,
&
r1
,
&
r2
);
...
...
@@ -3768,24 +3681,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_2
);
break
;
case
0x54
:
/* N R1,D2(X2,B2) [RX] */
case
0x56
:
/* O R1,D2(X2,B2) [RX] */
case
0x57
:
/* X R1,D2(X2,B2) [RX] */
insn
=
ld_code4
(
env
,
s
->
pc
);
tmp
=
decode_rx
(
s
,
insn
,
&
r1
,
&
x2
,
&
b2
,
&
d2
);
tmp2
=
tcg_temp_new_i64
();
tmp32_1
=
load_reg32
(
r1
);
tmp32_2
=
tcg_temp_new_i32
();
tcg_gen_qemu_ld32u
(
tmp2
,
tmp
,
get_mem_index
(
s
));
tcg_gen_trunc_i64_i32
(
tmp32_2
,
tmp2
);
gen_and_or_xor_i32
(
opc
,
tmp32_1
,
tmp32_2
);
store_reg32
(
r1
,
tmp32_1
);
set_cc_nz_u32
(
s
,
tmp32_1
);
tcg_temp_free_i64
(
tmp
);
tcg_temp_free_i64
(
tmp2
);
tcg_temp_free_i32
(
tmp32_1
);
tcg_temp_free_i32
(
tmp32_2
);
break
;
case
0x58
:
/* l r1, d2(x2, b2) */
insn
=
ld_code4
(
env
,
s
->
pc
);
tmp
=
decode_rx
(
s
,
insn
,
&
r1
,
&
x2
,
&
b2
,
&
d2
);
...
...
@@ -4723,6 +4618,12 @@ static ExitStatus op_add(DisasContext *s, DisasOps *o)
return
NO_EXIT
;
}
static
ExitStatus
op_and
(
DisasContext
*
s
,
DisasOps
*
o
)
{
tcg_gen_and_i64
(
o
->
out
,
o
->
in1
,
o
->
in2
);
return
NO_EXIT
;
}
static
ExitStatus
op_mul
(
DisasContext
*
s
,
DisasOps
*
o
)
{
tcg_gen_mul_i64
(
o
->
out
,
o
->
in1
,
o
->
in2
);
...
...
@@ -4736,12 +4637,24 @@ static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
return
NO_EXIT
;
}
static
ExitStatus
op_or
(
DisasContext
*
s
,
DisasOps
*
o
)
{
tcg_gen_or_i64
(
o
->
out
,
o
->
in1
,
o
->
in2
);
return
NO_EXIT
;
}
static
ExitStatus
op_sub
(
DisasContext
*
s
,
DisasOps
*
o
)
{
tcg_gen_sub_i64
(
o
->
out
,
o
->
in1
,
o
->
in2
);
return
NO_EXIT
;
}
static
ExitStatus
op_xor
(
DisasContext
*
s
,
DisasOps
*
o
)
{
tcg_gen_xor_i64
(
o
->
out
,
o
->
in1
,
o
->
in2
);
return
NO_EXIT
;
}
/* ====================================================================== */
/* The "Cc OUTput" generators. Given the generated output (and in some cases
the original inputs), update the various cc data structures in order to
...
...
@@ -4767,6 +4680,17 @@ static void cout_addu64(DisasContext *s, DisasOps *o)
gen_op_update3_cc_i64
(
s
,
CC_OP_ADDU_64
,
o
->
in1
,
o
->
in2
,
o
->
out
);
}
static
void
cout_nz32
(
DisasContext
*
s
,
DisasOps
*
o
)
{
tcg_gen_ext32u_i64
(
cc_dst
,
o
->
out
);
gen_op_update1_cc_i64
(
s
,
CC_OP_NZ
,
cc_dst
);
}
static
void
cout_nz64
(
DisasContext
*
s
,
DisasOps
*
o
)
{
gen_op_update1_cc_i64
(
s
,
CC_OP_NZ
,
o
->
out
);
}
static
void
cout_subs32
(
DisasContext
*
s
,
DisasOps
*
o
)
{
gen_op_update3_cc_i64
(
s
,
CC_OP_SUB_32
,
o
->
in1
,
o
->
in2
,
o
->
out
);
...
...
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