SiFive RISC-V GPIO Device
QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: NFabien Chouteau <chouteau@adacore.com> Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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hw/riscv/sifive_gpio.c
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hw/riscv/trace-events
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include/hw/riscv/sifive_gpio.h
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