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10055562
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体验新版 GitCode,发现更多精彩内容 >>
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10055562
编写于
11月 19, 2009
作者:
P
Paul Brook
浏览文件
操作
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电子邮件补丁
差异文件
ARM Cortex-A9 cpu support
Basic Cortex-A9 support. Signed-off-by:
N
Paul Brook
<
paul@codesourcery.com
>
上级
60011498
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
36 addition
and
1 deletion
+36
-1
target-arm/cpu.h
target-arm/cpu.h
+1
-0
target-arm/helper.c
target-arm/helper.c
+35
-1
未找到文件。
target-arm/cpu.h
浏览文件 @
10055562
...
@@ -389,6 +389,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
...
@@ -389,6 +389,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM1136_R2 0x4107b362
#define ARM_CPUID_ARM1136_R2 0x4107b362
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8 0x410fc080
#define ARM_CPUID_CORTEXA8 0x410fc080
#define ARM_CPUID_CORTEXA9 0x410fc090
#define ARM_CPUID_CORTEXM3 0x410fc231
#define ARM_CPUID_CORTEXM3 0x410fc231
#define ARM_CPUID_ANY 0xffffffff
#define ARM_CPUID_ANY 0xffffffff
...
...
target-arm/helper.c
浏览文件 @
10055562
...
@@ -9,6 +9,12 @@
...
@@ -9,6 +9,12 @@
#include "qemu-common.h"
#include "qemu-common.h"
#include "host-utils.h"
#include "host-utils.h"
static
uint32_t
cortexa9_cp15_c0_c1
[
8
]
=
{
0x1031
,
0x11
,
0x000
,
0
,
0x00100103
,
0x20000000
,
0x01230000
,
0x00002111
};
static
uint32_t
cortexa9_cp15_c0_c2
[
8
]
=
{
0x00101111
,
0x13112111
,
0x21232041
,
0x11112131
,
0x00111142
,
0
,
0
,
0
};
static
uint32_t
cortexa8_cp15_c0_c1
[
8
]
=
static
uint32_t
cortexa8_cp15_c0_c1
[
8
]
=
{
0x1031
,
0x11
,
0x400
,
0
,
0x31100003
,
0x20000000
,
0x01202000
,
0x11
};
{
0x1031
,
0x11
,
0x400
,
0
,
0x31100003
,
0x20000000
,
0x01202000
,
0x11
};
...
@@ -101,6 +107,27 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
...
@@ -101,6 +107,27 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env
->
cp15
.
c0_ccsid
[
1
]
=
0x2007e01a
;
/* 16k L1 icache. */
env
->
cp15
.
c0_ccsid
[
1
]
=
0x2007e01a
;
/* 16k L1 icache. */
env
->
cp15
.
c0_ccsid
[
2
]
=
0xf0000000
;
/* No L2 icache. */
env
->
cp15
.
c0_ccsid
[
2
]
=
0xf0000000
;
/* No L2 icache. */
break
;
break
;
case
ARM_CPUID_CORTEXA9
:
set_feature
(
env
,
ARM_FEATURE_V6
);
set_feature
(
env
,
ARM_FEATURE_V6K
);
set_feature
(
env
,
ARM_FEATURE_V7
);
set_feature
(
env
,
ARM_FEATURE_AUXCR
);
set_feature
(
env
,
ARM_FEATURE_THUMB2
);
set_feature
(
env
,
ARM_FEATURE_VFP
);
set_feature
(
env
,
ARM_FEATURE_VFP3
);
set_feature
(
env
,
ARM_FEATURE_VFP_FP16
);
set_feature
(
env
,
ARM_FEATURE_NEON
);
set_feature
(
env
,
ARM_FEATURE_THUMB2EE
);
env
->
vfp
.
xregs
[
ARM_VFP_FPSID
]
=
0x41034000
;
/* Guess */
env
->
vfp
.
xregs
[
ARM_VFP_MVFR0
]
=
0x11110222
;
env
->
vfp
.
xregs
[
ARM_VFP_MVFR1
]
=
0x01111111
;
memcpy
(
env
->
cp15
.
c0_c1
,
cortexa9_cp15_c0_c1
,
8
*
sizeof
(
uint32_t
));
memcpy
(
env
->
cp15
.
c0_c2
,
cortexa9_cp15_c0_c2
,
8
*
sizeof
(
uint32_t
));
env
->
cp15
.
c0_cachetype
=
0x80038003
;
env
->
cp15
.
c0_clid
=
(
1
<<
27
)
|
(
1
<<
24
)
|
3
;
env
->
cp15
.
c0_ccsid
[
0
]
=
0xe00fe015
;
/* 16k L1 dcache. */
env
->
cp15
.
c0_ccsid
[
1
]
=
0x200fe015
;
/* 16k L1 icache. */
break
;
case
ARM_CPUID_CORTEXM3
:
case
ARM_CPUID_CORTEXM3
:
set_feature
(
env
,
ARM_FEATURE_V6
);
set_feature
(
env
,
ARM_FEATURE_V6
);
set_feature
(
env
,
ARM_FEATURE_THUMB2
);
set_feature
(
env
,
ARM_FEATURE_THUMB2
);
...
@@ -287,6 +314,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
...
@@ -287,6 +314,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
{
ARM_CPUID_ARM11MPCORE
,
"arm11mpcore"
},
{
ARM_CPUID_ARM11MPCORE
,
"arm11mpcore"
},
{
ARM_CPUID_CORTEXM3
,
"cortex-m3"
},
{
ARM_CPUID_CORTEXM3
,
"cortex-m3"
},
{
ARM_CPUID_CORTEXA8
,
"cortex-a8"
},
{
ARM_CPUID_CORTEXA8
,
"cortex-a8"
},
{
ARM_CPUID_CORTEXA9
,
"cortex-a9"
},
{
ARM_CPUID_TI925T
,
"ti925t"
},
{
ARM_CPUID_TI925T
,
"ti925t"
},
{
ARM_CPUID_PXA250
,
"pxa250"
},
{
ARM_CPUID_PXA250
,
"pxa250"
},
{
ARM_CPUID_PXA255
,
"pxa255"
},
{
ARM_CPUID_PXA255
,
"pxa255"
},
...
@@ -1633,7 +1661,11 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
...
@@ -1633,7 +1661,11 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
case
3
:
/* TLB type register. */
case
3
:
/* TLB type register. */
return
0
;
/* No lockable TLB entries. */
return
0
;
/* No lockable TLB entries. */
case
5
:
/* CPU ID */
case
5
:
/* CPU ID */
return
env
->
cpu_index
;
if
(
ARM_CPUID
(
env
)
==
ARM_CPUID_CORTEXA9
)
{
return
env
->
cpu_index
|
0x80000900
;
}
else
{
return
env
->
cpu_index
;
}
default:
default:
goto
bad_reg
;
goto
bad_reg
;
}
}
...
@@ -1697,6 +1729,8 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
...
@@ -1697,6 +1729,8 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
return
1
;
return
1
;
case
ARM_CPUID_CORTEXA8
:
case
ARM_CPUID_CORTEXA8
:
return
2
;
return
2
;
case
ARM_CPUID_CORTEXA9
:
return
0
;
default:
default:
goto
bad_reg
;
goto
bad_reg
;
}
}
...
...
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