aspeed/smc: Add DMA calibration settings
When doing calibration, the SPI clock rate in the CE0 Control Register and the read delay cycles in the Read Timing Compensation Register are set using bit[11:4] of the DMA Control Register. Signed-off-by: NCédric Le Goater <clg@kaod.org> Acked-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190904070506.1052-7-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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