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    target-mips: flush QEMU TLB when disabling 64-bit addressing · f93c3a8d
    Leon Alrae 提交于
    CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit
    Kernel/Supervisor/User Segments. If bit is cleared an access to
    corresponding segment should generate Address Error Exception.
    
    However, the guest may still be able to access some pages belonging to
    the disabled 64-bit segment because we forget to flush QEMU TLB.
    
    This patch fixes it.
    Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
    f93c3a8d
cpu.h 32.9 KB