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    target/ppc: support for 32-bit carry and overflow · dd09c361
    Nikunj A Dadhania 提交于
    POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
    and corresponding defines.
    
    Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
    is updated.
    
    Arithmetic instructions:
        * Addition and Substractions:
    
            addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme,
            addze, and subfze always updates CA and CA32.
    
            => CA reflects the carry out of bit 0 in 64-bit mode and out of
               bit 32 in 32-bit mode.
            => CA32 reflects the carry out of bit 32 independent of the
               mode.
    
            => SO and OV reflects overflow of the 64-bit result in 64-bit
               mode and overflow of the low-order 32-bit result in 32-bit
               mode
            => OV32 reflects overflow of the low-order 32-bit independent of
               the mode
    
        * Multiply Low and Divide:
    
            For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits
            reflects overflow of the 64-bit result
    
            For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits
            reflects overflow of the 32-bit result
    
         * Negate with OE=1 (nego)
    
           For 64-bit mode if the register RA contains
           0x8000_0000_0000_0000, OV and OV32 are set to 1.
    
           For 32-bit mode if the register RA contains 0x8000_0000, OV and
           OV32 are set to 1.
    Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com>
    Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
    dd09c361
translate.c 244.3 KB