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    target-arm: Define exception record for AArch64 exceptions · abf1172f
    Peter Maydell 提交于
    For AArch32 exceptions, the only information provided about
    the cause of an exception is the individual exception type (data
    abort, undef, etc), which we store in cs->exception_index. For
    AArch64, the CPU provides much more detail about the cause of
    the exception, which can be found in the syndrome register.
    Create a set of fields in CPUARMState which must be filled in
    whenever an exception is raised, so that exception entry can
    correctly fill in the syndrome register for the guest.
    This includes the information which in AArch32 appears in
    the DFAR and IFAR (fault address registers) and the DFSR
    and IFSR (fault status registers) for data aborts and
    prefetch aborts, since if we end up taking the MMU fault
    to AArch64 rather than AArch32 this will need to end up
    in different system registers.
    
    This patch does a refactoring which moves the setting of the
    AArch32 DFAR/DFSR/IFAR/IFSR from the point where the exception
    is raised to the point where it is taken. (This is no change
    for cores with an MMU, retains the existing clearly incorrect
    behaviour for ARM946 of trashing the MP access permissions
    registers which share the c5_data and c5_insn state fields,
    and has no effect for v7M because we don't implement its
    MPU fault status or address registers.)
    
    As a side effect of the cleanup we fix a bug in the AArch64
    linux-user mode code where we were passing a 64 bit fault
    address through the 32 bit c6_data/c6_insn fields: it now
    goes via the always-64-bit exception.vaddress.
    Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
    Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
    abf1172f
main.c 136.9 KB