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由 Peter Crosthwaite 提交于
The data_count variable was being reset on every transfer, including DMA transfer resumptions. This is incorrect, it should only be set on a new command. Manifests as a bug when using ADMA and there is a timer delay between ADMA frames where the fifo is left in a non empty state. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Message-id: 15a98609cc32315211b0963091a8efd67522e160.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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