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    Makefile: use $(MAKE) variable · b98a3bae
    Philippe Mathieu-Daudé 提交于
    For some systems (i.e. FreeBSD) the default 'make' is not compatible with the
    GNU extensions used by QEMU makefiles.
    
    Calling the GNU make (gmake) works, however the help displayed refers to the
    host 'make' and copy/paste leads to lot of unobvious errors:
    
      $ gmake check-help
      [...]
       make check                Run all tests
    
      $ make check
      make: "Makefile" line 28: Missing dependency operator
      make: "Makefile" line 37: Need an operator
      make: "Makefile" line 41: warning: duplicate script for target "git-submodule-update" ignored
      make: "rules.mak" line 70: warning: duplicate script for target "%.o" ignored
      make: Unknown modifier ' '
      make: Unclosed substitution for eval modules (= missing)
      make: "tests/Makefile.include" line 24: Variable/Value missing from "export"
      make: "tests/" line 1: warning: Zero byte read from file, skipping rest of line.
      make: "tests/" line 1: Need an operator
      make: "Makefile" line 660: warning: duplicate script for target "ifneq" ignored
      make: "Makefile" line 78: warning: using previous script for "ifneq" defined here
      make: Fatal errors encountered -- cannot continue
    
    Using the $(MAKE) variable, the help displayed is consistent with the 'make'
    program used.
    Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
    Reviewed-by: NEric Blake <eblake@redhat.com>
    Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
    b98a3bae
Makefile.include 43.5 KB