-
由 Peter Maydell 提交于
Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
5a157588