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    target-arm: A64: Implement PMULL instruction · a984e42c
    Peter Maydell 提交于
    Implement the PMULL instruction; this is the last unimplemented insn
    in the three-reg-diff group.
    
    Note that PMULL with size 3 is considered part of the AES part
    of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
    in the v8 ARM ARM), so it isn't necessary to burn an extra feature
    bit on it, even though we're using more feature bits than a single
    "crypto extension present/not present" toggle.
    Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
    Reviewed-by: NRichard Henderson <rth@twiddle.net>
    Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org
    a984e42c
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