Two bugs about delay slot handlings are fixed.

- After an exception occurred in delay slot, the branch instruction
  before delay slot should be executed again. To judge such re-execution
  is necessery or not, delay slot status is kept in SH4 CPU data structure.
- When a branch instruction is placed at the end of memory segment,
  the delay slot is placed at the start of next memory segment.
  It means delay slot comes to the start of a translation block.
  In such occasion, DELAY_SLOT_CLAREME flag is used to transmit status
  between translation blocks. When an exception occurs on this kind of
  delay slot, DELAY_SLOT_CLEARME flag cause a status confusion in exception
  handling. DELAY_SLOT_CLEARME flag should be cleared on exceptions.

And some items are added to CPU status dump.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5066 c046a42c-6fe2-441c-8c8c-71466251a162