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由 Paul Burton 提交于
Support moving the GCR base address & updating the CPU's CP0 CMGCRBase register appropriately. This is required if a platform needs to move its GCRs away from other memory, as the MIPS Boston development board does to avoid its flash memory. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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