- 26 3月, 2020 1 次提交
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由 Christian Ehrhardt 提交于
One of the mitigation methods for TAA[1] is to disable TSX support on the host system. Linux added a mechanism to disable TSX globally through the kernel command line, and many Linux distributions now default to tsx=off. This makes existing CPU models that have HLE and RTM enabled not usable anymore. Add new versions of all CPU models that have the HLE and RTM features enabled, that can be used when TSX is disabled in the host system. On systems disabling the features without those types defined in cpu-maps users end up without modern CPU types in the list of usable CPUs to use in the likes of virsh domcapabilities or tools higher in the stack like virt-manager. This adds: -Cascadelake-Server-noTSX -Icelake-Client-noTSX -Icelake-Server-noTSX -Skylake-Server-noTSX-IBRS -Skylake-Client-noTSX-IBRS Introduced in QEMU by commit v4.2.0-rc2-3-g9ab2237f19 (function) and commit v4.2.0-rc2-4-g02fa60d101 (names) References: [1] TAA, TSX asynchronous Abort: https://software.intel.com/security-software-guidance/insights/deep-dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous-abort https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html Fixes: https://bugs.launchpad.net/ubuntu/+source/libvirt/+bug/1853200Signed-off-by: NChristian Ehrhardt <christian.ehrhardt@canonical.com> Message-Id: <20200310104806.2723-2-christian.ehrhardt@canonical.com> Reviewed-by: NJiri Denemark <jdenemar@redhat.com>
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- 07 1月, 2020 1 次提交
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由 Jiri Denemark 提交于
Introduced in QEMU by commit v4.1.0-266-g80db491da4. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 16 12月, 2019 1 次提交
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由 Ani Sinha 提交于
Qemu commit e900135dcfb67 ("i386: Add CPUID bit for CLZERO and XSAVEERPTR") adds support for CLZERO CPUID bit. This commit extends support for this CPUID bit into libvirt. Signed-off-by: NAni Sinha <ani.sinha@nutanix.com> Message-Id: <1575371352-99055-1-git-send-email-ani.sinha@nutanix.com> Reviewed-by: NJiri Denemark <jdenemar@redhat.com>
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- 13 12月, 2019 3 次提交
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由 Yingle Hou 提交于
Add Hygon Dhyana CPU model to the processor model. Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com> Signed-off-by: NYingle Hou <houyingle@hygon.cn>
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由 Jiri Denemark 提交于
CVE-2019-11135 When TSX_CTRL bit of IA32_ARCH_CAPABILITIES MSR is set to 1, the CPU supports IA32_TSX_CTRL MSR which can be used to disable and/or mask TSX. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
CVE-2019-11135 CPUs with TAA_NO bit of IA32_ARCH_CAPABILITIES MSR set to 1 are not vulnerable to TSX Asynchronous Abort and passing this bit to a guest may avoid unnecessary mitigations. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 13 11月, 2019 2 次提交
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由 Jiri Denemark 提交于
The pconfig feature was enabled in QEMU by accident in 3.1.0. All other newer versions do not support it and it was removed from the Icelake-Server CPU model in QEMU. We don't normally change our CPU models even when QEMU does so to avoid breaking migrations between different versions of libvirt. But we can safely do so in this specific case. QEMU never supported enabling pconfig so any domain which was able to start has pconfig disabled. With a small compatibility hack which explicitly disables pconfig when CPU model equals Icelake-Server in migratable domain definition, only one migration scenario stays broken (and there's nothing we can do about it): from any host to a host with libvirt < 5.10.0 and QEMU > 3.1.0. https://bugzilla.redhat.com/show_bug.cgi?id=1749672Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
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由 Jiri Denemark 提交于
QEMU does not support setting this feature on the command line anymore. We don't need to explain why it is not included in CPU models then. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
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- 08 11月, 2019 1 次提交
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由 Andrea Bolognani 提交于
The file was introduced in be03587a, but it was not added to $(cpumap_DATA) at the time and so it didn't show up in the distribution archive. Signed-off-by: NAndrea Bolognani <abologna@redhat.com>
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- 07 11月, 2019 1 次提交
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由 Andrea Bolognani 提交于
The only feature we care about for the moment is SVE, which can be controlled both with a coarse granularity by turning it on/off completely and with a finer granularity by enabling/disabling individual vector lengths. Signed-off-by: NAndrea Bolognani <abologna@redhat.com> Tested-by: NAndrew Jones <drjones@redhat.com> Reviewed-by: NMichal Privoznik <mprivozn@redhat.com>
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- 20 6月, 2019 1 次提交
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 15 5月, 2019 1 次提交
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由 Jiri Denemark 提交于
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091 The bit is set when microcode provides the mechanism to invoke a flush of various exploitable CPU buffers by invoking the VERW instruction. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
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- 25 4月, 2019 1 次提交
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由 Jiri Denemark 提交于
Added in QEMU by v2.12.0-481-g0da0fb0628 (released in 3.0). Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 14 4月, 2019 1 次提交
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由 Michal Privoznik 提交于
In 2878278c we've added new cpu model but we've forgot to distribute the XML file it comes in. Signed-off-by: NMichal Privoznik <mprivozn@redhat.com>
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- 13 4月, 2019 1 次提交
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由 Jiri Denemark 提交于
Introduced in QEMU 3.1.0 by commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8 Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 12 4月, 2019 1 次提交
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由 Andrea Bolognani 提交于
Vim has trouble figuring out the filetype automatically because the name doesn't follow existing conventions; annotations like the ones we already have in Makefile.ci help it out. Signed-off-by: NAndrea Bolognani <abologna@redhat.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
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- 09 4月, 2019 1 次提交
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由 Pavel Hrdina 提交于
The later is the correct CPU model name. Signed-off-by: NPavel Hrdina <phrdina@redhat.com>
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- 05 3月, 2019 10 次提交
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
This fixes several CPUs which were incorrectly detected as Skylake-Client. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
This fixes several CPUs which were incorrectly detected as a different CPU model. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
The family/model numbers are nice for humans or for comparing with /proc/cpuinfo, but sometimes there's a need to see the CPUID representation of the signature. Let's add it into a comment for each signature in out cpu_map XMLs as the conversion is not exactly straightforward. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 10 1月, 2019 1 次提交
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由 Jiri Denemark 提交于
The feature was added to QEMU in 3.1.0 and it is currently blocking migration, which is expected to change in the future. Luckily 3.1.0 is new enough to give us migratability hints on each feature via query-cpu-model-expension, which means we don't need to use the "migratable" attribute on the CPU map XML. The kernel calls this feature arch_capabilities and RHEL/CentOS 7.* use arch-facilities. Apparently some CPU test files were gathered with the RHEL version of QEMU. Let's update the test files to avoid possible confusion about the correct naming. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 18 12月, 2018 1 次提交
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由 Jiri Denemark 提交于
QEMU commit v3.1.0-4-g0e89165829 KVM patch: https://lore.kernel.org/lkml/20181205191956.31480-1-ehabkost@redhat.com/Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 03 10月, 2018 1 次提交
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由 Jiri Denemark 提交于
In commit v4.7.0-168-g993d85ae I introduced two Icelake CPU models, but failed to actually include them in the CPU map index. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 19 9月, 2018 2 次提交
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由 Jiri Denemark 提交于
Introduced in QEMU by commit v3.0.0-156-g8a11c62da9. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
QEMU commits: e37a5c7fa4 (v2.12.0) i386: Add Intel Processor Trace feature support c2f193b538 (v2.7.0) target-i386: Add support for UMIP and RDPID CPUID bits aff9e6e46a (v2.12.0) x86/cpu: Enable new SSE/AVX/AVX512 cpu features f77543772d (v2.9.0) x86: add AVX512_VPOPCNTDQ features 5131dc433d (v3.1.0) i386: Add CPUID bit for PCONFIG 59a80a19ca (v3.1.0) i386: Add CPUID bit for WBNOINVD Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 28 8月, 2018 3 次提交
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由 Daniel P. Berrangé 提交于
Reviewed-by: NJiri Denemark <jdenemar@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
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由 Daniel P. Berrangé 提交于
Reviewed-by: NJiri Denemark <jdenemar@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
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由 Daniel P. Berrangé 提交于
In preparation for splitting up the CPU map data file, move it into a dedicated directory of its own. Reviewed-by: NJiri Denemark <jdenemar@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
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