- 03 10月, 2018 1 次提交
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由 Jiri Denemark 提交于
In commit v4.7.0-168-g993d85ae I introduced two Icelake CPU models, but failed to actually include them in the CPU map index. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 28 8月, 2018 3 次提交
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由 Daniel P. Berrangé 提交于
Reviewed-by: NJiri Denemark <jdenemar@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
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由 Daniel P. Berrangé 提交于
Reviewed-by: NJiri Denemark <jdenemar@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
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由 Daniel P. Berrangé 提交于
In preparation for splitting up the CPU map data file, move it into a dedicated directory of its own. Reviewed-by: NJiri Denemark <jdenemar@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
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- 04 7月, 2018 1 次提交
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由 Daniel P. Berrangé 提交于
AMD x86 CPUs have two separate ways to mitigate the Speculative Store Bypass hardware flaw. In current processors only non-architectural MSRs are available, and so hypervisors must expose a virtualized MSR and CPU flag "virt-ssbd" (CPUID Function 8000_0008, EBX[25]=1). In future processors AMD will provide an architectural MSR, indicated by existance of the CPUID Function 8000_0008, EBX[24]=1, to which QEMU has given the name "amd-ssbd". The "amd-ssbd" flag should be used in preference to "virt-ssbd", if it is available, since it provides improved performance. For virtual machine configuration, both should be exposed when available, to allow for maximal guest OS compatibility as not all guests yet support both. If future processes are not vulnerable to the flaw, this will be indicated by the existance of CPUID Function 8000_0008, EBX[26]=1, to which QEMU has given the name "amd-no-ssb". See also 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf from: https://bugzilla.kernel.org/show_bug.cgi?id=199889 Note that neither amd-ssbd or amd-no-ssb will be reported by the kernel in /proc/cpuinfo. It knows about these CPUID bits and does the right thing, but doesn't report their existance as distinct flags in /proc/cpuinfo. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
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- 22 5月, 2018 2 次提交
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由 Daniel P. Berrangé 提交于
Some AMD processors only support a non-architectural means of enabling Speculative Store Bypass Disable. To allow simplified handling in virtual environments, hypervisors will expose an architectural definition through CPUID bit 0x80000008_EBX[25]. This needs to be exposed to guest OS running on AMD x86 hosts to allow them to protect against CVE-2018-3639. Note that since this CPUID bit won't be present in the host CPUID results on physical hosts, it will not be enabled automatically in guests configured with "host-model" CPU unless using QEMU version >= 2.9.0. Thus for older versions of QEMU, this feature must be manually enabled using policy=force. Guests using the "host-passthrough" CPU mode do not need special handling. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Reviewed-by: NJiri Denemark <jdenemar@redhat.com>
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由 Daniel P. Berrangé 提交于
New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Reviewed-by: NJiri Denemark <jdenemar@redhat.com>
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- 25 1月, 2018 1 次提交
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由 Shaohe Feng 提交于
We can start qemu with a "cpu,+la57" to set 57-bit vitrual address space. So VM can be aware that it need to enable 5-level paging. Corresponding QEMU commits: al57 6c7c3c21f95dd9af8a0691c0dd29b07247984122
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- 18 1月, 2018 12 次提交
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由 Jiri Denemark 提交于
This is a variant of EPYC with indirect branch prediction protection. The only difference between EPYC and EPYC-IBPB is the added "ibpb" feature. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Skylake-Server with indirect branch prediction protection. The only difference between Skylake-Server and Skylake-Server-IBRS is the added "spec-ctrl" feature. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Skylake-Client with indirect branch prediction protection. The only difference between Skylake-Client and Skylake-Client-IBRS is the added "spec-ctrl" feature. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Broadwell with indirect branch prediction protection. The only difference between Broadwell and Broadwell-IBRS is the added "spec-ctrl" feature. The Broadwell-IBRS model in QEMU is a bit different since Broadwell got several additional features since we added it in cpu_map.xml: abm, arat, f16c, rdrand, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Broadwell-noTSX with indirect branch prediction protection. The only difference between Broadwell-noTSX and Broadwell-noTSX-IBRS is the added "spec-ctrl" feature. The Broadwell-noTSX-IBRS model in QEMU is a bit different since Broadwell-noTSX got several additional features since we added it in cpu_map.xml: abm, arat, f16c, rdrand, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Haswell with indirect branch prediction protection. The only difference between Haswell and Haswell-IBRS is the added "spec-ctrl" feature. The Haswell-IBRS model in QEMU is a bit different since Haswell got several additional features since we added it in cpu_map.xml: arat, abm, f16c, rdrand, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Haswell-noTSX with indirect branch prediction protection. The only difference between Haswell-noTSX and Haswell-noTSX-IBRS is the added "spec-ctrl" feature. The Haswell-noTSX-IBRS model in QEMU is a bit different since Haswell-noTSX got several additional features since we added it in cpu_map.xml: arat, abm, f16c, rdrand, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of IvyBridge with indirect branch prediction protection. The only difference between IvyBridge and IvyBridge-IBRS is the added "spec-ctrl" feature. The IvyBridge-IBRS model in QEMU is a bit different since IvyBridge got several additional features since we added it in cpu_map.xml: arat, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of SandyBridge with indirect branch prediction protection. The only difference between SandyBridge and SandyBridge-IBRS is the added "spec-ctrl" feature. The SandyBridge-IBRS model in QEMU is a bit different since SandyBridge got several additional features since we added it in cpu_map.xml: arat, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Westmere with indirect branch prediction protection. The only difference between Westmere and Westmere-IBRS is the added "spec-ctrl" feature. The Westmere-IBRS model in QEMU is a bit different since Westmere got several additional features since we added it in cpu_map.xml: arat, pclmuldq, vme Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
This is a variant of Nehalem with indirect branch prediction protection. The only difference between Nehalem and Nehalem-IBRS is the added "spec-ctrl" feature. Thus the diff matches QEMU, but the new CPU model itself is different. The QEMU's versions of both models contain "vme" feature, while this feature is missing in libvirt's models. While we can't change the existing Nehalem CPU model, we could add "vme" to Nehalem-IBRS to make it similar to QEMU, but doing so would fool our CPU detecting code so that any Nehalem CPU with "vme" feature would be detected as Nehalem-IBRS CPU without spec-ctrl. Not adding "vme" to Nehalem-IBRS is safe as QEMU will just provide the feature anyway, which matches what happens with Nehalem (and new enough machine types). Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Paolo Bonzini 提交于
Added in QEMU commits TBD and TBD. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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- 03 11月, 2017 1 次提交
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由 Jiri Denemark 提交于
Linux kernel shows our "cmt" feature as "cqm". Let's mention the name in the cpu_map.xml to make it easier to find. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJohn Ferlan <jferlan@redhat.com>
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- 18 9月, 2017 2 次提交
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由 Jiri Denemark 提交于
Available since QEMU 2.10.0 (specifically commit v2.9.0-2233-g53f9a6f45f). Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
The features were added to QEMU by commit v2.4.0-1690-gf7fda28094 as Skylake Server features. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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- 07 9月, 2017 1 次提交
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由 Brijesh Singh 提交于
Add a new CPU model called 'EPYC' to model processors from AMD EPYC family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx). The following features bits have been added/removed compare to Opteron_G5 Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw, fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha xsaveopt, xsavec, xgetbv1, arat Removed: xop, fma4, tbm The patch is depend on EPYC CPU model supported introduced in qemu [1] [1] https://patchwork.kernel.org/patch/9902205/ Cc: Tom Lendacky <Thomas.Lendacky@amd.com> Signed-off-by: NBrijesh Singh <brijesh.singh@amd.com> Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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- 04 8月, 2017 1 次提交
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CPUID leaf 7 is sub-leaf aware. Add missing attribute. Signed-off-by: NMarek Marczykowski-Górecki <marmarek@invisiblethingslab.com> Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 09 5月, 2017 1 次提交
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由 Kothapally Madhu Pavan 提交于
As POWER9 model is not available in cpu_map.xml virsh capabilities donot display the cpu model and vendor details. This patch provides those details
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- 06 12月, 2016 1 次提交
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由 Lin Ma 提交于
qemu commit: f74eefe0 https://lwn.net/Articles/667156/Signed-off-by: NLin Ma <lma@suse.com>
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- 05 12月, 2016 1 次提交
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由 Lin Ma 提交于
These features are included: AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW and AVX512_4FMAPS. qemu commits: cc728d14 and 95ea69fb Signed-off-by: NLin Ma <lma@suse.com>
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- 30 11月, 2016 2 次提交
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由 Jiri Denemark 提交于
We can't change feature names for compatibility reasons even if they contain typos or other software uses different names for the same features. By adding alternative spellings in our CPU map we at least allow anyone to grep for them and find the correct libvirt's name. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
They didn't really help anything. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 25 6月, 2016 1 次提交
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由 Qiaowei Ren 提交于
Some Intel processor families (e.g. the Intel Xeon processor E5 v3 family) introduced some PQos (Platform Qos) features, including CMT (Cache Monitoring technology) and MBM (Memory Bandwidth Monitoring), to monitor or control shared resource. This patch add them into x86 part of cpu_map.xml to be used for applications based on libvirt to get cpu capabilities. For example, Nova in OpenStack schedules guests based on the CPU features that the host has. Signed-off-by: NQiaowei Ren <qiaowei.ren@intel.com>
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- 17 6月, 2016 2 次提交
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由 Jiri Denemark 提交于
Our current detection code uses just the number of CPU features which need to be added/removed from the CPU model to fully describe the CPUID data. The smallest number wins. But this may sometimes generate wrong results as one can see from the fixed test cases. This patch modifies the algorithm to prefer the CPU model with matching signature even if this model results in a longer list of additional features. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
The CPU model was implemented in QEMU by commit f6f949e929. The change to i7-5600U is wrong since it's a 5th generation CPU, i.e., Broadwell rather than Skylake, but that's just the result of our CPU detection code (which is fixed by the following commit). Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 09 6月, 2016 6 次提交
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由 Jiri Denemark 提交于
Implemented in QEMU by commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
This was implemented in QEMU by commit 0bb0b2d2fe7f645dda. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
As a side effect this changes the order of CPU features in XMLs generated by libvirt, but that's not a big deal since the order there is insignificant. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
For two reasons: - 0x00000001 is very similar to 0x80000001, but 0x01 is visually different - 0x01 format is consistent with CPUID manual Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
This patch makes our CPUID handling code up-to-date with the current specification found in Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2A http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.htmlSigned-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
CPUID instruction normally takes its parameter from EAX, but sometimes ECX is used as an additional parameter. Let's rename 'function' to 'eax_in' in preparation for adding 'ecx_in'. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 16 5月, 2016 1 次提交
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由 Alexander Burluka 提交于
Corresponding QEMU commits: clflushopt f7fda280948a5e74aeb076ef346b991ecb173c56 tsc_adjust 7b458bfd12a71b3da6b531daedc417492c9334e0 Signed-off-by: NAlexander Burluka <aburluka@virtuozzo.com>
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