- 15 5月, 2019 1 次提交
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由 Jiri Denemark 提交于
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091 The bit is set when microcode provides the mechanism to invoke a flush of various exploitable CPU buffers by invoking the VERW instruction. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
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- 13 4月, 2019 2 次提交
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由 Jiri Denemark 提交于
Introduced in QEMU 3.1.0 by commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8 Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 18 12月, 2018 1 次提交
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由 Jiri Denemark 提交于
QEMU commit v3.1.0-4-g0e89165829 KVM patch: https://lore.kernel.org/lkml/20181205191956.31480-1-ehabkost@redhat.com/Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NJán Tomko <jtomko@redhat.com>
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- 19 9月, 2018 1 次提交
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由 Jiri Denemark 提交于
QEMU commits: e37a5c7fa4 (v2.12.0) i386: Add Intel Processor Trace feature support c2f193b538 (v2.7.0) target-i386: Add support for UMIP and RDPID CPUID bits aff9e6e46a (v2.12.0) x86/cpu: Enable new SSE/AVX/AVX512 cpu features f77543772d (v2.9.0) x86: add AVX512_VPOPCNTDQ features 5131dc433d (v3.1.0) i386: Add CPUID bit for PCONFIG 59a80a19ca (v3.1.0) i386: Add CPUID bit for WBNOINVD Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 18 1月, 2018 2 次提交
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由 Jiri Denemark 提交于
This is a variant of Skylake-Server with indirect branch prediction protection. The only difference between Skylake-Server and Skylake-Server-IBRS is the added "spec-ctrl" feature. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
The CPU contains the updated microcode for CVE-2017-5715. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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- 18 9月, 2017 3 次提交
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由 Jiri Denemark 提交于
Available since QEMU 2.10.0 (specifically commit v2.9.0-2233-g53f9a6f45f). Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
The features were added to QEMU by commit v2.4.0-1690-gf7fda28094 as Skylake Server features. Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com> Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
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- 14 3月, 2017 1 次提交
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由 Jiri Denemark 提交于
This element is only allowed for host CPUs. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 24 2月, 2017 1 次提交
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由 Jiri Denemark 提交于
While "x86" is a CPU sub driver name, it is not a recognized name of any architecture known to libvirt. Let's use "x86_64" prefix which can be used with virArch APIs. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 17 6月, 2016 1 次提交
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由 Jiri Denemark 提交于
The CPU model was implemented in QEMU by commit f6f949e929. The change to i7-5600U is wrong since it's a 5th generation CPU, i.e., Broadwell rather than Skylake, but that's just the result of our CPU detection code (which is fixed by the following commit). Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 09 6月, 2016 7 次提交
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由 Jiri Denemark 提交于
Implemented in QEMU by commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
This was implemented in QEMU by commit 0bb0b2d2fe7f645dda. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
As a side effect this changes the order of CPU features in XMLs generated by libvirt, but that's not a big deal since the order there is insignificant. Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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由 Jiri Denemark 提交于
Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
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- 05 9月, 2014 1 次提交
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由 Ján Tomko 提交于
Commit fba6bc47 introduced support for the 'invtsc' feature, which blocks migration. We should not include it in the host-model CPU by default, because it's intended to be used with migration. https://bugzilla.redhat.com/show_bug.cgi?id=1138221
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- 17 1月, 2012 3 次提交
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由 Jiri Denemark 提交于
VIR_DOMAIN_XML_UPDATE_CPU flag for virDomainGetXMLDesc may be used to get updated custom mode guest CPU definition in case it depends on host CPU. This patch implements the same behavior for host-model and host-passthrough CPU modes.
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由 Jiri Denemark 提交于
The mode can be either of "custom" (default), "host-model", "host-passthrough". The semantics of each mode is described in the following examples: - guest CPU is a default model with specified topology: <cpu> <topology sockets='1' cores='2' threads='1'/> </cpu> - guest CPU matches selected model: <cpu mode='custom' match='exact'> <model>core2duo</model> </cpu> - guest CPU should be a copy of host CPU as advertised by capabilities XML (this is a short cut for manually copying host CPU specification from capabilities to domain XML): <cpu mode='host-model'/> In case a hypervisor does not support the exact host model, libvirt automatically falls back to a closest supported CPU model and removes/adds features to match host. This behavior can be disabled by <cpu mode='host-model'> <model fallback='forbid'/> </cpu> - the same as previous returned by virDomainGetXMLDesc with VIR_DOMAIN_XML_UPDATE_CPU flag: <cpu mode='host-model' match='exact'> <model fallback='allow'>Penryn</model> --+ <vendor>Intel</vendor> | <topology sockets='2' cores='4' threads='1'/> + copied from <feature policy='require' name='dca'/> | capabilities XML <feature policy='require' name='xtpr'/> | ... --+ </cpu> - guest CPU should be exactly the same as host CPU even in the aspects libvirt doesn't model (such domain cannot be migrated unless both hosts contain exactly the same CPUs): <cpu mode='host-passthrough'/> - the same as previous returned by virDomainGetXMLDesc with VIR_DOMAIN_XML_UPDATE_CPU flag: <cpu mode='host-passthrough' match='minimal'> <model>Penryn</model> --+ copied from caps <vendor>Intel</vendor> | XML but doesn't <topology sockets='2' cores='4' threads='1'/> | describe all <feature policy='require' name='dca'/> | aspects of the <feature policy='require' name='xtpr'/> | actual guest CPU ... --+ </cpu>
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由 Jiri Denemark 提交于
In case a hypervisor doesn't support the exact CPU model requested by a domain XML, we automatically fallback to a closest CPU model the hypervisor supports (and make sure we add/remove any additional features if needed). This patch adds 'fallback' attribute to model element, which can be used to disable this automatic fallback.
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- 01 12月, 2010 1 次提交
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由 Jiri Denemark 提交于
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