1. 18 1月, 2018 8 次提交
    • J
      cpu: Add Broadwell-noTSX-IBRS CPU model · 49bffcb3
      Jiri Denemark 提交于
      This is a variant of Broadwell-noTSX with indirect branch prediction
      protection. The only difference between Broadwell-noTSX and
      Broadwell-noTSX-IBRS is the added "spec-ctrl" feature.
      
      The Broadwell-noTSX-IBRS model in QEMU is a bit different since
      Broadwell-noTSX got several additional features since we added it in
      cpu_map.xml:
          abm, arat, f16c, rdrand, vme, xsaveopt
      
      Adding them only to the -IBRS variant would confuse our CPU detection
      code.
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      49bffcb3
    • J
      cpu: Add Haswell-IBRS CPU model · 7f83eefa
      Jiri Denemark 提交于
      This is a variant of Haswell with indirect branch prediction protection.
      The only difference between Haswell and Haswell-IBRS is the added
      "spec-ctrl" feature.
      
      The Haswell-IBRS model in QEMU is a bit different since Haswell got
      several additional features since we added it in cpu_map.xml:
          arat, abm, f16c, rdrand, vme, xsaveopt
      
      Adding them only to the -IBRS variant would confuse our CPU detection
      code.
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      7f83eefa
    • J
      cpu: Add Haswell-noTSX-IBRS CPU model · 7dd85ff6
      Jiri Denemark 提交于
      This is a variant of Haswell-noTSX with indirect branch prediction
      protection. The only difference between Haswell-noTSX and
      Haswell-noTSX-IBRS is the added "spec-ctrl" feature.
      
      The Haswell-noTSX-IBRS model in QEMU is a bit different since
      Haswell-noTSX got several additional features since we added it in
      cpu_map.xml:
          arat, abm, f16c, rdrand, vme, xsaveopt
      
      Adding them only to the -IBRS variant would confuse our CPU detection
      code.
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      7dd85ff6
    • J
      cpu: Add IvyBridge-IBRS CPU model · 203c92e9
      Jiri Denemark 提交于
      This is a variant of IvyBridge with indirect branch prediction
      protection. The only difference between IvyBridge and IvyBridge-IBRS is
      the added "spec-ctrl" feature.
      
      The IvyBridge-IBRS model in QEMU is a bit different since IvyBridge got
      several additional features since we added it in cpu_map.xml:
          arat, vme, xsaveopt
      
      Adding them only to the -IBRS variant would confuse our CPU detection
      code.
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      203c92e9
    • J
      cpu: Add SandyBridge-IBRS CPU model · 30b381cf
      Jiri Denemark 提交于
      This is a variant of SandyBridge with indirect branch prediction
      protection. The only difference between SandyBridge and SandyBridge-IBRS
      is the added "spec-ctrl" feature.
      
      The SandyBridge-IBRS model in QEMU is a bit different since SandyBridge
      got several additional features since we added it in cpu_map.xml:
          arat, vme, xsaveopt
      
      Adding them only to the -IBRS variant would confuse our CPU detection
      code.
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      30b381cf
    • J
      cpu: Add Westmere-IBRS CPU model · 2e3b220a
      Jiri Denemark 提交于
      This is a variant of Westmere with indirect branch prediction
      protection. The only difference between Westmere and Westmere-IBRS is
      the added "spec-ctrl" feature.
      
      The Westmere-IBRS model in QEMU is a bit different since Westmere got
      several additional features since we added it in cpu_map.xml:
          arat, pclmuldq, vme
      
      Adding them only to the -IBRS variant would confuse our CPU detection
      code.
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      2e3b220a
    • J
      cpu: Add Nehalem-IBRS CPU model · 6b7e7d1c
      Jiri Denemark 提交于
      This is a variant of Nehalem with indirect branch prediction protection.
      The only difference between Nehalem and Nehalem-IBRS is the added
      "spec-ctrl" feature.
      
      Thus the diff matches QEMU, but the new CPU model itself is different.
      The QEMU's versions of both models contain "vme" feature, while this
      feature is missing in libvirt's models. While we can't change the
      existing Nehalem CPU model, we could add "vme" to Nehalem-IBRS to make
      it similar to QEMU, but doing so would fool our CPU detecting code so
      that any Nehalem CPU with "vme" feature would be detected as
      Nehalem-IBRS CPU without spec-ctrl. Not adding "vme" to Nehalem-IBRS is
      safe as QEMU will just provide the feature anyway, which matches what
      happens with Nehalem (and new enough machine types).
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      6b7e7d1c
    • P
      cpu: add CPU features for indirect branch prediction protection · 8b605530
      Paolo Bonzini 提交于
      Added in QEMU commits TBD and TBD.
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      Reviewed-by: NPavel Hrdina <phrdina@redhat.com>
      8b605530
  2. 10 1月, 2018 2 次提交
  3. 04 1月, 2018 2 次提交
  4. 03 11月, 2017 2 次提交
  5. 18 10月, 2017 1 次提交
  6. 16 10月, 2017 5 次提交
  7. 12 10月, 2017 1 次提交
  8. 18 9月, 2017 8 次提交
  9. 07 9月, 2017 1 次提交
  10. 04 8月, 2017 1 次提交
  11. 13 7月, 2017 1 次提交
  12. 13 6月, 2017 2 次提交
  13. 07 6月, 2017 1 次提交
  14. 09 5月, 2017 1 次提交
  15. 19 4月, 2017 2 次提交
  16. 07 4月, 2017 2 次提交