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  1. 13 4月, 2019 1 次提交
  3. 09 4月, 2019 1 次提交
  5. 03 10月, 2018 1 次提交
  7. 28 8月, 2018 3 次提交
  9. 04 7月, 2018 1 次提交
    • D
      cpu: add 'amd-ssbd' and 'amd-no-ssb' CPU features (CVE-2018-3639) · 2625722c
      由 Daniel P. Berrangé 提交于 
      AMD x86 CPUs have two separate ways to mitigate the Speculative Store
Bypass hardware flaw. In current processors only non-architectural MSRs
are available, and so hypervisors must expose a virtualized MSR and CPU
flag "virt-ssbd" (CPUID Function 8000_0008, EBX[25]=1).

In future processors AMD will provide an architectural MSR, indicated by
existance of the CPUID Function 8000_0008, EBX[24]=1, to which QEMU has
given the name "amd-ssbd".

The "amd-ssbd" flag should be used in preference to "virt-ssbd", if it
is available, since it provides improved performance. For virtual
machine configuration, both should be exposed when available, to allow
for maximal guest OS compatibility as not all guests yet support both.

If future processes are not vulnerable to the flaw, this will be
indicated by the existance of CPUID Function 8000_0008, EBX[26]=1,
to which QEMU has given the name "amd-no-ssb".

See also 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
from:

  https://bugzilla.kernel.org/show_bug.cgi?id=199889

Note that neither amd-ssbd or amd-no-ssb will be reported by the kernel
in /proc/cpuinfo. It knows about these CPUID bits and does the right thing,
but doesn't report their existance as distinct flags in /proc/cpuinfo.
Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com>
      2625722c
  11. 22 5月, 2018 2 次提交
  13. 25 1月, 2018 1 次提交
    • S
      cpu: Add support for al57 Intel features · e7cb9c4e
      由 Shaohe Feng 提交于 
      We can start qemu with a "cpu,+la57" to set 57-bit vitrual address
space. So VM can be aware that it need to enable 5-level paging.

Corresponding QEMU commits:
        al57 6c7c3c21f95dd9af8a0691c0dd29b07247984122
      e7cb9c4e
  15. 18 1月, 2018 12 次提交
  17. 03 11月, 2017 1 次提交
  19. 18 9月, 2017 2 次提交
  21. 07 9月, 2017 1 次提交
  23. 04 8月, 2017 1 次提交
  25. 09 5月, 2017 1 次提交
  27. 06 12月, 2016 1 次提交
  29. 05 12月, 2016 1 次提交
  31. 30 11月, 2016 2 次提交
  33. 25 6月, 2016 1 次提交
    • Q
      cpu_map.xml: add cmt/mbm feature to x86 · f294b83e
      由 Qiaowei Ren 提交于 
      Some Intel processor families (e.g. the Intel Xeon processor E5 v3
family) introduced some PQos (Platform Qos) features, including CMT
(Cache Monitoring technology) and MBM (Memory Bandwidth Monitoring),
to monitor or control shared resource. This patch add them into x86
part of cpu_map.xml to be used for applications based on libvirt to
get cpu capabilities. For example, Nova in OpenStack schedules guests
based on the CPU features that the host has.
Signed-off-by: NQiaowei Ren <qiaowei.ren@intel.com>
      f294b83e
  35. 17 6月, 2016 2 次提交
    • J
      cpu_x86: Use signature in CPU detection code · 5a9221b9
      由 Jiri Denemark 提交于 
      Our current detection code uses just the number of CPU features which
need to be added/removed from the CPU model to fully describe the CPUID
data. The smallest number wins. But this may sometimes generate wrong
results as one can see from the fixed test cases. This patch modifies
the algorithm to prefer the CPU model with matching signature even if
this model results in a longer list of additional features.
Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      5a9221b9
    • J
      cpu: Add Skylake-Client x86 CPU model · 2f3ccdf0
      由 Jiri Denemark 提交于 
      The CPU model was implemented in QEMU by commit f6f949e929.

The change to i7-5600U is wrong since it's a 5th generation CPU, i.e.,
Broadwell rather than Skylake, but that's just the result of our CPU
detection code (which is fixed by the following commit).
Signed-off-by: NJiri Denemark <jdenemar@redhat.com>
      2f3ccdf0
  37. 09 6月, 2016 5 次提交