提交 3fe07443 编写于 作者: X Xu Yandong 提交者: zhanghailiang

tests: add baseline test cases for arm CPU

add baseline test cases for aarch64
Signed-off-by: NXu Yandong <xuyandong2@huawei.com>
上级 cea36e98
......@@ -1194,6 +1194,13 @@ mymain(void)
DO_TEST_BASELINE(VIR_ARCH_PPC64, "same-model", 0, 0);
DO_TEST_BASELINE(VIR_ARCH_PPC64, "legacy", 0, -1);
DO_TEST_BASELINE(VIR_ARCH_AARCH64, "incompatible-vendors", 0, -1);
DO_TEST_BASELINE(VIR_ARCH_AARCH64, "no-vendor", 0, 0);
DO_TEST_BASELINE(VIR_ARCH_AARCH64, "no-feature", 0, 0);
DO_TEST_BASELINE(VIR_ARCH_AARCH64, "one-feature", 0, 0);
DO_TEST_BASELINE(VIR_ARCH_AARCH64, "no-compatible-feature", 0, 0);
DO_TEST_BASELINE(VIR_ARCH_AARCH64, "one-compatible-feature", 0, 0);
/* CPU features */
DO_TEST_HASFEATURE(VIR_ARCH_X86_64, "host", "vmx", YES);
DO_TEST_HASFEATURE(VIR_ARCH_X86_64, "host", "lm", YES);
......
<cpuTest>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<vendor>ARM</vendor>
<feature name='fp'/>
<feature name='asimd'/>
<feature name='aes'/>
<feature name='pmull'/>
<feature name='sha1'/>
<feature name='sha2'/>
<feature name='crc32'/>
</cpu>
<cpu>
<arch>aarch64</arch>
<model>cortex-a72</model>
<vendor>Hisilicon</vendor>
<feature name='fp'/>
<feature name='asimd'/>
<feature name='aes'/>
<feature name='pmull'/>
<feature name='sha1'/>
<feature name='sha2'/>
<feature name='crc32'/>
</cpu>
</cpuTest>
<cpu mode='custom' match='exact'>
<model fallback='forbid'>cortex-a57</model>
<vendor>ARM</vendor>
</cpu>
<cpuTest>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<vendor>ARM</vendor>
<feature name='fp'/>
<feature name='asimd'/>
<feature name='pmull'/>
<feature name='sha2'/>
<feature name='crc32'/>
</cpu>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<vendor>ARM</vendor>
<feature name='aes'/>
<feature name='sha1'/>
</cpu>
</cpuTest>
<cpu mode='custom' match='exact'>
<model fallback='forbid'>cortex-a57</model>
<vendor>ARM</vendor>
</cpu>
<cpuTest>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<vendor>ARM</vendor>
</cpu>
</cpuTest>
<cpuTest>
<cpu>
<arch>aarch64</arch>
<vendor>ARM</vendor>
<feature name='fp'/>
<feature name='asimd'/>
<feature name='aes'/>
<feature name='pmull'/>
<feature name='sha1'/>
<feature name='sha2'/>
<feature name='crc32'/>
</cpu>
</cpuTest>
<cpu mode='custom' match='exact'>
<model fallback='forbid'>cortex-a57</model>
<feature policy='require' name='fp'/>
<feature policy='require' name='asimd'/>
<feature policy='require' name='aes'/>
<feature policy='require' name='pmull'/>
<feature policy='require' name='sha1'/>
<feature policy='require' name='sha2'/>
<feature policy='require' name='crc32'/>
</cpu>
<cpuTest>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<feature name='fp'/>
<feature name='asimd'/>
<feature name='aes'/>
<feature name='pmull'/>
<feature name='sha1'/>
<feature name='sha2'/>
<feature name='crc32'/>
</cpu>
</cpuTest>
<cpu mode='custom' match='exact'>
<model fallback='forbid'>cortex-a57</model>
<vendor>ARM</vendor>
<feature policy='require' name='sha1'/>
</cpu>
<cpuTest>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<vendor>ARM</vendor>
<feature name='fp'/>
<feature name='asimd'/>
<feature name='aes'/>
<feature name='pmull'/>
<feature name='sha1'/>
<feature name='sha2'/>
<feature name='crc32'/>
</cpu>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<vendor>ARM</vendor>
<feature name='sha1'/>
</cpu>
</cpuTest>
<cpu mode='custom' match='exact'>
<model fallback='forbid'>cortex-a57</model>
<vendor>ARM</vendor>
<feature policy='require' name='fp'/>
</cpu>
<cpuTest>
<cpu>
<arch>aarch64</arch>
<model>cortex-a57</model>
<vendor>ARM</vendor>
<feature name='fp'/>
</cpu>
</cpuTest>
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