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  1. 28 6月, 2007 16 次提交
  3. 25 6月, 2007 17 次提交
  5. 14 6月, 2007 7 次提交
    • D
      [POWERPC] Fix problems with device tree representation of TSI-1xx bridges · e58ca3de
      由 David Gibson 提交于 
      This fixes some problems with the way the some things
represented in the device tree for the Holly and Taiga boards.  This
means changes both to the dts files, and to the code which
instantiates the tsi108 ethernet platform devices based on the device
tree.

	- First, and most importantly, the ethernet PHYs are given
with an identical 'reg' property.  This reg currently encodes the
accessible register used to initiate mdio interaction with the PHYs,
rather than a meaningful address on the parent bus (mdio in this
case), which is incorrect.  Instead we give the address of these
registers as 'reg' in the mdio node itself, and encode the ID of each
phy in their 'reg' propertyies.
	- Currently the platform device constructor enables a
workaround in the tsi108 ethernet driver based on the compatible
property of the PHY.  This is incorrect, because the workaround in
question is necessary due to the board's wiring of the PHY, not the
model of PHY itself.  This patch alters the constructor to instead
enable the workaround based on a new special property in the PHY node.
	- The compatible properties on a number of nodes in the device
tree are insufficiently precise.  In particular the PHYs give only
"bcm54xx", which is broken, since there are many bcm54xx PHY models,
and they have differences which matter.  The mdio had a compatible
property of "tsi-ethernet" identical to the ethernet MAC nodes, which
doesn't make sense.  The ethernet, i2c, bridge and PCI nodes were
given only as "tsi-*" which is somewhat inprecise, we replace with
"tsi108-*" in the case of Taiga (which has a TSI108 bridge), and
"tsi109-*", "tsi108-*" in the case of Holly (which has a TSI109
bridge).
	- We remove some "model" properties from the ethernets on
Taiga board which were neither useful nor adequately precise.
	- On Holly we change to using a dtc label instead of a full
path to reference the MPIC node, which makes the dts a little more
readable.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      e58ca3de
    • D
      [POWERPC] Don't store a command line in the Holly device tree · e60c526f
      由 David Gibson 提交于 
      Currently, the Holly device tree includes a bootargs property in
/chosen, which gives a commandline.  This is somewhat inconvenient,
because it means an alternative default command line can't be given in
the kernel config - the value obtained from the dts via the
bootwrapper will always override CONFIG_CMDLINE.

This removes the command line from the dts, and instead puts the
same command line as a default in holly_defconfig.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      e60c526f
    • D
      [POWERPC] Consolidate cuboot initialization code · 85aecac8
      由 David Gibson 提交于 
      The various cuboot platforms (i.e. pre-device tree aware u-boot for
83xx, 85xx and Ebony) share a certain amount of code for parsing the
boot parameters.  To a certain extent that's inevitable, since they
platforms have different definitions of the bd_t structure.  However,
with some macro work and a helper function, this patch improves the
situation a bit.

In the process, this fixes a bug on Ebony, which was incorrectly
handling the parameters passed form u-boot for the command line (the
bug was copied from 83xx and 85xx which have subsequently been fixed).
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      85aecac8
    • D
      [POWERPC] Derive ebc ranges property from EBC registers · b2ba34f3
      由 David Gibson 提交于 
      In the device tree for Ebony, the 'ranges' property in the node for
the EBC bridge shows the mappings from the chip select / address lines
actually used for the EBC peripherals into the address space of the
OPB.  At present, these mappings are hardcoded in ebony.dts for the
mappings set up by the OpenBIOS firmware when it configures the EBC
bridge.

This replaces the hardcoded mappings with code in the zImage to
read the EBC configuration registers and create an appropriate ranges
property based on them.  This should make the zImage and kernel more
robust to changes in firmware configuration.  In particular, some of
the Ebony's DIP switches can change the effective address of the Flash
and other peripherals in OPB space.  With this patch, the kernel will
be able to cope with at least some of the possible variations.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      b2ba34f3
    • D
      [POWERPC] Factor zImage's 44x reset code out of ebony.c · 11123346
      由 David Gibson 提交于 
      The ebony_exit() function which resets the Ebony board should in fact
be common to most if not all 44x boards.  This moves the function out
into 44x.c, renaming it, so it can be used by other 44x platforms.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      11123346
    • D
      [POWERPC] Merge CPU features pertaining to icache coherency · 4508dc21
      由 David Gibson 提交于 
      Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially).  It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.

In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).

This tries to clarify the situation a little.  The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified.  We check this, instead of
SPLIT_ID_CACHE nearly everywhere.

The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200.  In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature.  The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.

This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      4508dc21
    • D
      [POWERPC] Kill typedef-ed structs for hash PTEs and BATs · 8e561e7e
      由 David Gibson 提交于 
      Using typedefs to rename structure types if frowned on by CodingStyle.
However, we do so for the hash PTE structure on both ppc32 (where it's
called "PTE") and ppc64 (where it's called "hpte_t").  On ppc32 we
also have such a typedef for the BATs ("BAT").

This removes this unhelpful use of typedefs, in the process
bringing ppc32 and ppc64 closer together, by using the name "struct
hash_pte" in both cases.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      8e561e7e