1. 15 1月, 2015 32 次提交
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  8. 28 11月, 2014 2 次提交
    • F
      ASoC: sgtl5000: Allow 8kHz playback in codec slave mode · 2a4cfd10
      Fabio Estevam 提交于
      When trying to play a 8kHz file with codec in slave mode we get the following
      error on a mx28evk:
      
      $ aplay -Dhw:0,0 stereo_8k.wav
      Playing WAVE 'stereo_8k.wav' : Signed 16 bit Little Endian, Rate 8000 Hz, Stereo
      [   21.218647] sgtl5000 0-000a: PLL not supported in slave mode
      [   21.224559] sgtl5000 0-000a: 128 ratio is not supported. SYS_MCLK needs to be 256, 384 or 512 * fs
      [   21.233687] sgtl5000 0-000a: ASoC: can't set sgtl5000 hw params: -22
      aplay: set_params:1123: Unable to install hw params:
      
      This error happens because we are using 'sys_fs' instead of 'frame_rate' in the
      valid ratio check.
      
      Use the real'frame_rate' so that the ratio is correctly calculated and the
      playback can run.
      
      sgtl5000 codec manual states that in 'Synchronous SYS_MCLK input' mode that the
      following SYS_CLK frequencies are allowed: 256*fs, 384*fs, 512*fs.
      
      , where fs is the sampling frequency, which can be in the range of:
      8, 11.025, 16, 22.5, 32, 44.1, 48, 96 kHz.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      2a4cfd10
    • F
      ASoC: sgtl5000: Remove MCLK restriction · d819ce96
      Fabio Estevam 提交于
      According to the sgtl5000 datasheet the MCLK frequency range restriction of
      8 to 27 MHz only applies when the PLL is used - synchronous SYS_MCLK input mode.
      
      When running the codec as slave, the master should generate MCLK in the range of
      256*fs, 384*fs or 512*fs, which is called asynchronous SYS_MCLK input mode.
      
      In asynchronous SYS_MCLK we cannot have the 8 to 27 MHz check because if we
      want to play a 8KHz sample rate track, with a MCLK of 8k * 512 = 4.096MHz the
      current check would return -EINVAL, which is not correct.
      
      Remove the 8 to 27MHz frequency check, since this only applies to the
      synchronous SYS_MCLK input case.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      d819ce96