- 31 5月, 2014 7 次提交
-
-
由 Arnd Bergmann 提交于
This makes it possible to enable the Exynos platform as part of a multiplatform kernel. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Sachin Kamat 提交于
Instead of repeating the Kconfig entries for every SoC, move them under ARCH_EXYNOS3, 4 and 5 and move the entries common to 3, 4 and 5 under ARCH_EXYNOS. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Tarek Dakhran 提交于
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: NTarek Dakhran <t.dakhran@samsung.com> Signed-off-by: NVyacheslav Tyrtov <v.tyrtov@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Chanwoo Choi 提交于
This patch fix the offset of CPU boot address and don't need to send smc call of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes WFE in secure mode. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Chanwoo Choi 提交于
This patch add Exynos3250's SoC ID. Exynos 3250 is SoC that is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7 dual cores and has a target speed of 1.0GHz. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Arun Kumar K 提交于
Exynos5800 is an octa core SoC which is based on the 5420 platform. This patch adds the basic support for it in the mach-exynos. Signed-off-by: NArun Kumar K <arun.kk@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Pankaj Dubey 提交于
This patch add basic arch side support for exynos5260 SoC. Note that this is required to enable build for clock driver. Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
- 30 5月, 2014 1 次提交
-
-
由 Georgi Djakov 提交于
Add information about the APQ8084 debug UART physical and virtual addresses in the DEBUG_QCOM_UARTDM Kconfig help section. Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com> Signed-off-by: NKumar Gala <galak@codeaurora.org>
-
- 27 5月, 2014 2 次提交
-
-
由 Arnd Bergmann 提交于
The sunxi reset controller code is only used with sun6i (a31). After the platform has been split up into per-soc options, it's now possible to build it without the reset controller code, so the base platform init must not call into the reset driver if that is turned off at compile time. Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Heiko Stübner 提交于
With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore to reference the relevant smp_ops in the board file, but instead it can simply be set by the enable-method property of the cpu nodes. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NOlof Johansson <olof@lixom.net>
-
- 26 5月, 2014 9 次提交
-
-
由 Heiko Stuebner 提交于
Move debug-macro.S from mach/include to include/debug where all other common debug macros are. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Heiko Stuebner 提交于
This removes the need for mach/-headers in the debug macro. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Heiko Stuebner 提交于
Using the lowlevel debug uart is a corner case - even more so in a multiplatform environment. So it seems reasonable to simply let the developer set the appropriate uart type for the debugged SoC. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Heiko Stuebner 提交于
addruart from the generic debug macro is doing exactly the same using the common lowlevel uart definition, so there is no cause for this special casing for s3c24xx. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Sachin Kamat 提交于
Exynos specific macros and declarations have been moved to mach-exynos. Inclusion of plat/cpu.h is no more necessary. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Sachin Kamat 提交于
Move Exynos specific macros to mach-exynos from plat-samsung to avoid unnecessary dependency on plat based header files. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Sachin Kamat 提交于
'exynos_subsys' has no users. Remove this code. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Sachin Kamat 提交于
Group all files compiled under common config option together. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
由 Leela Krishna Amudala 提交于
A common macro v7_exit_coherency_flush available which does the below tasks in the seqeunce. -clearing C bit -clearing L1 cache -exit SMP -instruction and data synchronization So removing the local functions which does the same thing and use the macro instead. Signed-off-by: NLeela Krishna Amudala <leela.krishna@linaro.org> Acked-by: NNicolas Pitre <nico@linaro.org> [cw00.choi@samsung.com: tested on exynos3250 based board] Tested-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
-
- 24 5月, 2014 4 次提交
-
-
由 Anders Berg 提交于
Add the reset controller to the AXM5xx device tree. Signed-off-by: NAnders Berg <anders.berg@lsi.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Anders Berg 提交于
Add a defconfig file for the LSI Axxia family of devices (CONFIG_ARCH_AXXIA). Signed-off-by: NAnders Berg <anders.berg@lsi.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Anders Berg 提交于
Add device tree for the Amarillo validation board with an AXM5516 SoC. Signed-off-by: NAnders Berg <anders.berg@lsi.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Anders Berg 提交于
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15 cores (in a 4x4 cluster configuration). The cores within each cluster share an L2 cache, and the clusters are connected to each other via a CCN-504 cache coherent interconnect. This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located above 4GB in the memory map. Signed-off-by: NAnders Berg <anders.berg@lsi.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
- 23 5月, 2014 5 次提交
-
-
由 Maxime Ripard 提交于
The init_machine hook is now at its default value. We can remove it. Even though the sun4i and sun7i machines are nothing more than generic machines now, leave them in so that we won't have to add them back if needed, and so that the machine is still displayed in /proc/cpuinfo. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Maxime Ripard 提交于
Now that reset is handled either by the watchdog driver for the sun4i, sun5i and sun7i, and by a driver of its own for sun6i, we can remove it from the platform code. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NArnd Bergmann <arnd@arndb.de>
-
由 Andy Gross 提交于
Add missing PINCTRL selection. This enables selection of pinctrollers for Qualcomm processors. Signed-off-by: NAndy Gross <agross@codeaurora.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
-
由 Ivan T. Ivanov 提交于
Separate Qualcomm low-level debugging UART to two options. DEBUG_MSM_UART is used in earlier non-multi platform arches, like MSM7X00A, QSD8X50 and MSM7X30. DEBUG_QCOM_UARTDM is used in multi-plafrom arches and have embedded data mover. Make DEBUG_UART_PHYS and DEBUG_UART_BASE user adjustable by Kconfig menu. Signed-off-by: NIvan T. Ivanov <iivanov@mm-sol.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Tested-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
-
由 Srinivas Kandagatla 提交于
As some of the IPs on Qualcomm SOCs are based on ARM PrimeCell IPs. For example SDCC controller is PrimeCell MCI pl180. Adding this option will give flexibility to reuse the existing drivers as it is without major modifications. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
-
- 22 5月, 2014 6 次提交
-
-
由 Thomas Petazzoni 提交于
In the refactoring of the coherency fabric assembly code, a function called ll_get_cpuid() was created to factorize common logic between functions adding CPU to the SMP coherency group, enabling and disabling the coherency. However, the name of the function is highly misleading: ll_get_cpuid() makes one think tat it returns the ID of the CPU, i.e 0 for CPU0, 1 for CPU1, etc. In fact, this is not at all what this function returns: it returns a CPU mask for the current CPU, usable for the coherency fabric configuration and control registers. Therefore this commit renames this function to ll_get_coherency_cpumask(), and adds additional comments on top of the function to explain in more details what it does, and also how the endianess issue is handled. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-5-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Thomas Petazzoni 提交于
This commit makes no functional change, it only improves a bit the various code comments in mach-mvebu/coherency_ll.S, by fixing a few typos and adding a few more details. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-4-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Thomas Petazzoni 提交于
This commit does not make any functional change, it only fixes the indentation of a few assembly instructions in arch/arm/mach-mvebu/coherency_ll.S. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-3-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Thomas Petazzoni 提交于
As part of the introduction of the cpuidle support for Armada XP, the coherency code was significantly reworked, especially in the coherency_ll.S file. However, when the ll_get_cpuid function was created, the big-endian specific code that switches the endianess of the register was not updated properly. This patch fixes this code, and therefore makes big endian systems bootable again. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 2e8a5942 ("ARM: mvebu: Split low level functions to manipulate HW coherency") Reported-by: NKevin Hilman <khilman@linaro.org> Cc: Kevin Hilman <khilman@linaro.org> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Thomas Petazzoni 提交于
Commit b0063aad ("ARM: mvebu: use hardware I/O coherency also for PCI devices") added a reference to the pci_bus_type variable, but this variable is only available when CONFIG_PCI is enabled. Therefore, there is now a build failure in !CONFIG_PCI situations. This commit fixes that by enclosing the entire initcall into a IS_ENABLED(CONFIG_PCI) condition. Reported-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400598783-706-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Thomas Petazzoni 提交于
The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9 CPU core, the PL310 cache and the Marvell PCIe hardware block are affected a L2/PCIe deadlock caused by a system erratum when hardware I/O coherency is used. This deadlock can be avoided by mapping the PCIe memory areas as strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by removing the outer cache sync done in software. This is implemented in this patch by: * Registering a custom arch_ioremap_caller function that allows to make sure PCI memory regions are mapped MT_UNCACHED. * Adding at runtime the 'arm,io-coherent' property to the PL310 cache controller. This cannot be done permanently in the DT, because the hardware I/O coherency can only be enabled when CONFIG_SMP is enabled, in the current kernel situation. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400165974-9059-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
- 20 5月, 2014 6 次提交
-
-
由 Michal Simek 提交于
Enable ARCH_SUPPORTS_BIG_ENDIAN in Kconfig. zynq_secondary_trampoline is the first function that is called on secondary CPU. Reference: "ARM: mcpm: fix big endian issue in mcpm startup code" (sha1: 519ceb9f) Fix early printk support. Based on: "ARM: pl01x debug code endian fix" (sha1: 76e3faf1) Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
由 Michal Simek 提交于
Virtual address have to have the same offset within a 2MB aligned section of virtual/phycial address space. Fix uart0 virtual address to be align with physical one. Also remove UART_SIZE which is completely unused. Reported-by: NRuss Smith <russells@google.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
由 Michal Simek 提交于
Keep options sorted. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
由 Michal Simek 提交于
Provide information through SOC_BUS to user space. Silicon revision is provided through devcfg device. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
由 Nishanth Menon 提交于
Currently the files in /sys/devices/soc0/ show no information about DRA7. Few userspace programs do depend on this information to make SoC specific support. So update logic to detect the relevant information and provide to userspace. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
-
由 Dave Gerlach 提交于
In omap2_common_pm_late_init suspend_set_ops was called to set common suspend handling functions for all omap platforms. This created two problems. First, these suspend ops were being set for all platforms, regardless of whether or not suspend support has been integrated so in the case of AM33XX, suspend to mem was presented as available but failed every time. Second, some platforms will need to define a completely separate set of suspend ops, such as AM33XX, due to differences from previous omap platforms so there is no need to always set the common omap ops. This patch moves the suspend_set_ops call from omap2_common_pm_late_init into a separate function that then gets called in the omap*_pm_init functions for each platform. Signed-off-by: NDave Gerlach <d-gerlach@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
-