- 31 3月, 2022 1 次提交
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由 Kees Cook 提交于
To follow the existing per-arch conventions, rename "sp_in_global" to "current_stack_pointer". This will let it be used in non-arch places (like HARDENED_USERCOPY). Signed-off-by: NKees Cook <keescook@chromium.org> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 30 3月, 2022 1 次提交
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由 Fangrui Song 提交于
On ELF, (NOLOAD) sets the section type to SHT_NOBITS[1]. It is conceptually inappropriate for .plt, .got, and .got.plt sections which are always SHT_PROGBITS. In GNU ld, if PLT entries are needed, .plt will be SHT_PROGBITS anyway and (NOLOAD) will be essentially ignored. In ld.lld, since https://reviews.llvm.org/D118840 ("[ELF] Support (TYPE=<value>) to customize the output section type"), ld.lld will report a `section type mismatch` error (later changed to a warning). Just remove (NOLOAD) to fix the warning. [1] https://lld.llvm.org/ELF/linker_script.html As of today, "The section should be marked as not loadable" on https://sourceware.org/binutils/docs/ld/Output-Section-Type.html is outdated for ELF. Link: https://github.com/ClangBuiltLinux/linux/issues/1597 Fixes: ab1ef68e ("RISC-V: Add sections of PLT and GOT for kernel module") Reported-by: NNathan Chancellor <nathan@kernel.org> Signed-off-by: NFangrui Song <maskray@google.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 24 3月, 2022 1 次提交
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由 Jisheng Zhang 提交于
Replace the conditional compilation using "#ifdef CONFIG_KEXEC_CORE" by a check for "IS_ENABLED(CONFIG_KEXEC_CORE)", to simplify the code and increase compile coverage. Link: https://lkml.kernel.org/r/20211206160514.2000-3-jszhang@kernel.orgSigned-off-by: NJisheng Zhang <jszhang@kernel.org> Acked-by: NPalmer Dabbelt <palmer@rivosinc.com> Acked-by: NBaoquan He <bhe@redhat.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Borislav Petkov <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Eric W. Biederman <ebiederm@xmission.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will@kernel.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 23 3月, 2022 3 次提交
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由 David Hildenbrand 提交于
... and call node_dev_init() after memory_dev_init() from driver_init(), so before any of the existing arch/subsys calls. All online nodes should be known at that point: early during boot, arch code determines node and zone ranges and sets the relevant nodes online; usually this happens in setup_arch(). This is in line with memory_dev_init(), which initializes the memory device subsystem and creates all memory block devices. Similar to memory_dev_init(), panic() if anything goes wrong, we don't want to continue with such basic initialization errors. The important part is that node_dev_init() gets called after memory_dev_init() and after cpu_dev_init(), but before any of the relevant archs call register_cpu() to register the new cpu device under the node device. The latter should be the case for the current users of topology_init(). Link: https://lkml.kernel.org/r/20220203105212.30385-1-david@redhat.comSigned-off-by: NDavid Hildenbrand <david@redhat.com> Reviewed-by: NOscar Salvador <osalvador@suse.de> Tested-by: Anatoly Pugachev <matorola@gmail.com> (sparc64) Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Michal Hocko <mhocko@suse.com> Cc: Oscar Salvador <osalvador@suse.de> Cc: Mike Rapoport <rppt@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Anshuman Khandual 提交于
ARCH_WANT_GENERAL_HUGETLB config has duplicate definitions on platforms that subscribe it. Instead make it a generic config option which can be selected on applicable platforms when required. Link: https://lkml.kernel.org/r/1643718465-4324-1-git-send-email-anshuman.khandual@arm.comSigned-off-by: NAnshuman Khandual <anshuman.khandual@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Mike Kravetz <mike.kravetz@oracle.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Vincent Chen 提交于
Add calls to rseq_signal_deliver() and rseq_syscall() to introduce RSEQ support. 1. Call the rseq_signal_deliver() function to fixup on the pre-signal frame when a signal is delivered on top of a restartable sequence critical section. 2. Check that system calls are not invoked from within rseq critical sections by invoking rseq_signal() from ret_from_syscall(). With CONFIG_DEBUG_RSEQ, such behavior results in termination of the process with SIGSEGV. Signed-off-by: NVincent Chen <vincent.chen@sifive.com> Reviewed-by: NMathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 22 3月, 2022 4 次提交
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由 Atish Patra 提交于
The sscofpmf extension allows counter overflow and filtering for programmable counters. Enable the perf driver to handle the overflow interrupt. The overflow interrupt is a hart local interrupt. Thus, per cpu overflow interrupts are setup as a child under the root INTC irq domain. Signed-off-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Atish Patra 提交于
This patch adds all the definitions defined by the SBI PMU extension. Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Atish Patra 提交于
Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are accessible in S-mode. Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Atish Patra 提交于
The current perf implementation in RISC-V is not very useful as it can not count any events other than cycle/instructions. Moreover, perf record can not be used or the events can not be started or stopped. Remove the implementation now for a better platform driver in future that will implement most of the missing functionality. Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 18 3月, 2022 6 次提交
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由 Atish Patra 提交于
Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Same goes for the single letter extensions as well which prints the entire ISA string. Some of they may not be valid ISA extensions as well (e.g 'su') Parse only the valid & enabled ISA extension and print them. Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Atish Patra 提交于
The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Atish Patra 提交于
Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Tsukasa OI 提交于
Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Tested-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NTsukasa OI <research_trasio@irq.a4lg.com> [Improved commit text and comments] Signed-off-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Tsukasa OI 提交于
Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: NAtish Patra <atishp@rivosinc.com> [Fixed workaround for QEMU] Signed-off-by: NTsukasa OI <research_trasio@irq.a4lg.com> Tested-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Tsukasa OI 提交于
This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: NAnup Patel <anup@brainfault.org> Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NTsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 11 3月, 2022 11 次提交
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由 Anup Patel 提交于
The SBI v0.3 specification extends SBI HSM extension by adding SBI HSM suspend call and related HART states. This patch extends the KVM RISC-V HSM implementation to provide KVM guest a minimal SBI HSM suspend call which is equivalent to a WFI instruction. Signed-off-by: NAnup Patel <apatel@ventanamicro.com> Reviewed-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Anup Patel 提交于
The wait for interrupt (WFI) instruction emulation can share the VCPU halt logic with SBI HSM suspend emulation so this patch adds a common kvm_riscv_vcpu_wfi() function for this purpose. Signed-off-by: NAnup Patel <apatel@ventanamicro.com> Reviewed-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Anup Patel 提交于
We add defines related to SBI HSM suspend call and also update HSM states naming as-per the latest SBI specification. Signed-off-by: NAnup Patel <apatel@ventanamicro.com> Reviewed-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Anup Patel 提交于
The SBI v0.3 specification defines SRST (System Reset) extension which provides a standard poweroff and reboot interface. This patch implements SRST extension for the KVM Guest. Signed-off-by: NAnup Patel <apatel@ventanamicro.com> Reviewed-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Anup Patel 提交于
We rename kvm_sbi_system_shutdown() to kvm_riscv_vcpu_sbi_system_reset() and move it to vcpu_sbi.c so that it can be shared by SBI v0.1 shutdown and SBI v0.3 SRST extension. Signed-off-by: NAnup Patel <apatel@ventanamicro.com> Reviewed-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Anup Patel 提交于
We upgrade SBI spec version implemented by KVM RISC-V to v0.3 so that Guest kernel can probe and use SBI extensions added by the SBI v0.3 specification. Signed-off-by: NAnup Patel <apatel@ventanamicro.com> Reviewed-by: NAtish Patra <atishp@rivosinc.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Vincent Chen 提交于
Kernel uses __kvm_riscv_switch_to() and __kvm_switch_return() to switch the context of host kernel and guest kernel. Several CSRs belonging to the context will be read and written during the context switch. To ensure atomic read-modify-write control of CSR and ordering of CSR accesses, some hardware blocks flush the pipeline when writing a CSR. In this circumstance, grouping CSR executions together as much as possible can reduce the performance impact of the pipeline. Therefore, this commit reorders the CSR instructions to enhance the context switch performance.. Signed-off-by: NVincent Chen <vincent.chen@sifive.com> Suggested-by: NHsinyi Lee <hsinyi.lee@sifive.com> Suggested-by: NFu-Ching Yang <fu-ching.yang@sifive.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Yang Li 提交于
Eliminate the following coccicheck warning: ./arch/riscv/kvm/vcpu_sbi_v01.c:117:2-3: Unneeded semicolon Reported-by: NAbaci Robot <abaci@linux.alibaba.com> Signed-off-by: NYang Li <yang.lee@linux.alibaba.com> Signed-off-by: NAnup Patel <anup@brainfault.org>
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由 Emil Renner Berthing 提交于
RISC-V can do PC-relative jumps with a 32bit range using the following two instructions: auipc t0, imm20 ; t0 = PC + imm20 * 2^12 jalr ra, t0, imm12 ; ra = PC + 4, PC = t0 + imm12 Crucially both the 20bit immediate imm20 and the 12bit immediate imm12 are treated as two's-complement signed values. For this reason the immediates are usually calculated like this: imm20 = (offset + 0x800) >> 12 imm12 = offset & 0xfff ..where offset is the signed offset from the auipc instruction. When the 11th bit of offset is 0 the addition of 0x800 doesn't change the top 20 bits and imm12 considered positive. When the 11th bit is 1 the carry of the addition by 0x800 means imm20 is one higher, but since imm12 is then considered negative the two's complement representation means it all cancels out nicely. However, this addition by 0x800 (2^11) means an offset greater than or equal to 2^31 - 2^11 would overflow so imm20 is considered negative and result in a backwards jump. Similarly the lower range of offset is also moved down by 2^11 and hence the true 32bit range is [-2^31 - 2^11, 2^31 - 2^11) Signed-off-by: NEmil Renner Berthing <kernel@esmil.dk> Fixes: e2c0cdfb ("RISC-V: User-facing API") Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Michael T. Kloos 提交于
Rewrote the RISC-V memmove() assembly implementation. The previous implementation did not check memory alignment and it compared 2 pointers with a signed comparison. The misaligned memory access would cause the kernel to crash on systems that did not emulate it in firmware and did not support it in hardware. Firmware emulation is slow and may not exist. The RISC-V spec does not guarantee that support for misaligned memory accesses will exist. It should not be depended on. This patch now checks for XLEN granularity of co-alignment between the pointers. Failing that, copying is done by loading from the 2 contiguous and naturally aligned XLEN memory locations containing the overlapping XLEN sized data to be copied. The data is shifted into the correct place and binary or'ed together on each iteration. The result is then stored into the corresponding naturally aligned XLEN sized location in the destination. For unaligned data at the terminations of the regions to be copied or for copies less than (2 * XLEN) in size, byte copy is used. This patch also now uses unsigned comparison for the pointers and migrates to the newer assembler annotations from the now deprecated ones. Signed-off-by: NMichael T. Kloos <michael@michaelkloos.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Jisheng Zhang 提交于
The alternative mechanism needs runtime code patching, it can't work on XIP_KERNEL. And the errata workarounds are implemented via the alternative mechanism. So add !XIP_KERNEL dependency for alternative and erratas. Signed-off-by: NJisheng Zhang <jszhang@kernel.org> Fixes: 44c92257 ("RISC-V: enable XIP") Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 10 3月, 2022 5 次提交
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由 Conor Dooley 提交于
Add new peripherals to the MPFS, and enable them in the Icicle kit device tree: 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller. Signed-off-by: NConor Dooley <conor.dooley@microchip.com> Acked-by: NPalmer Dabbelt <palmer@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Conor Dooley 提交于
Assorted minor changes to the MPFS/Icicle kit device tree: - enable mmuart4 instead of mmuart0 - remove sifive pdma - split memory node to match updated fpga design - move stdout path to serial1 to avoid collision with bootloader running on the e51 Signed-off-by: NConor Dooley <conor.dooley@microchip.com> Acked-by: NPalmer Dabbelt <palmer@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Conor Dooley 提交于
Assorted minor changes to the MPFS/Icicle kit device tree: - rename serial to mmuart to match microchip documentation - move phy0 inside mac1 node to match phy configuration - add labels where missing (cpus, cache controller) - add missing address cells & interrupts to MACs Signed-off-by: NConor Dooley <conor.dooley@microchip.com> Acked-by: NPalmer Dabbelt <palmer@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Conor Dooley 提交于
Split the device tree for the Microchip MPFS into two sections by adding microchip-mpfs-fabric.dtsi, which contains peripherals contained in the FPGA fabric. Signed-off-by: NConor Dooley <conor.dooley@microchip.com> Acked-by: NPalmer Dabbelt <palmer@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Conor Dooley 提交于
Update the Microchip Icicle kit device tree by replacing clock related magic numbers with their defined counterparts. Signed-off-by: NConor Dooley <conor.dooley@microchip.com> Acked-by: NPalmer Dabbelt <palmer@rivosinc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 04 3月, 2022 7 次提交
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由 Niklas Cassel 提交于
Commit 67d96729 ("riscv: Update Canaan Kendryte K210 device tree") incorrectly removed two entries from the PLIC interrupt-controller node's interrupts-extended property. The PLIC driver cannot know the mapping between hart contexts and hart ids, so this information has to be provided by device tree, as specified by the PLIC device tree binding. The PLIC driver uses the interrupts-extended property, and initializes the hart context registers in the exact same order as provided by the interrupts-extended property. In other words, if we don't specify the S-mode interrupts, the PLIC driver will simply initialize the hart0 S-mode hart context with the hart1 M-mode configuration. It is therefore essential to specify the S-mode IRQs even though the system itself will only ever be running in M-mode. Re-add the S-mode interrupts, so that we get working IRQs on hart1 again. Cc: <stable@vger.kernel.org> Fixes: 67d96729 ("riscv: Update Canaan Kendryte K210 device tree") Signed-off-by: NNiklas Cassel <niklas.cassel@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Alexandre Ghiti 提交于
In sv48, the kasan inner regions are not aligned on PGDIR_SIZE and then when we populate the kasan linear mapping region, we clear the kasan vmalloc region which is in the same PGD. Fix this by copying the content of the kasan early pud after allocating a new PGD for the first time. Fixes: e8a62cc2 ("riscv: Implement sv48 support") Signed-off-by: NAlexandre Ghiti <alexandre.ghiti@canonical.com> Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Alexandre Ghiti 提交于
high_memory used to be initialized in mem_init, way after setup_bootmem. But a call to dma_contiguous_reserve in this function gives rise to the below warning because high_memory is equal to 0 and is used at the very beginning at cma_declare_contiguous_nid. It went unnoticed since the move of the kasan region redefined KERN_VIRT_SIZE so that it does not encompass -1 anymore. Fix this by initializing high_memory in setup_bootmem. ------------[ cut here ]------------ virt_to_phys used for non-linear address: ffffffffffffffff (0xffffffffffffffff) WARNING: CPU: 0 PID: 0 at arch/riscv/mm/physaddr.c:14 __virt_to_phys+0xac/0x1b8 Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 5.17.0-rc1-00007-ga68b89289e26 #27 Hardware name: riscv-virtio,qemu (DT) epc : __virt_to_phys+0xac/0x1b8 ra : __virt_to_phys+0xac/0x1b8 epc : ffffffff80014922 ra : ffffffff80014922 sp : ffffffff84a03c30 gp : ffffffff85866c80 tp : ffffffff84a3f180 t0 : ffffffff86bce657 t1 : fffffffef09406e8 t2 : 0000000000000000 s0 : ffffffff84a03c70 s1 : ffffffffffffffff a0 : 000000000000004f a1 : 00000000000f0000 a2 : 0000000000000002 a3 : ffffffff8011f408 a4 : 0000000000000000 a5 : 0000000000000000 a6 : 0000000000f00000 a7 : ffffffff84a03747 s2 : ffffffd800000000 s3 : ffffffff86ef4000 s4 : ffffffff8467f828 s5 : fffffff800000000 s6 : 8000000000006800 s7 : 0000000000000000 s8 : 0000000480000000 s9 : 0000000080038ea0 s10: 0000000000000000 s11: ffffffffffffffff t3 : ffffffff84a035c0 t4 : fffffffef09406e8 t5 : fffffffef09406e9 t6 : ffffffff84a03758 status: 0000000000000100 badaddr: 0000000000000000 cause: 0000000000000003 [<ffffffff8322ef4c>] cma_declare_contiguous_nid+0xf2/0x64a [<ffffffff83212a58>] dma_contiguous_reserve_area+0x46/0xb4 [<ffffffff83212c3a>] dma_contiguous_reserve+0x174/0x18e [<ffffffff83208fc2>] paging_init+0x12c/0x35e [<ffffffff83206bd2>] setup_arch+0x120/0x74e [<ffffffff83201416>] start_kernel+0xce/0x68c irq event stamp: 0 hardirqs last enabled at (0): [<0000000000000000>] 0x0 hardirqs last disabled at (0): [<0000000000000000>] 0x0 softirqs last enabled at (0): [<0000000000000000>] 0x0 softirqs last disabled at (0): [<0000000000000000>] 0x0 ---[ end trace 0000000000000000 ]--- Fixes: f7ae0233 ("riscv: Move KASAN mapping next to the kernel mapping") Signed-off-by: NAlexandre Ghiti <alexandre.ghiti@canonical.com> Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Alexandre Ghiti 提交于
__virt_to_phys function is called very early in the boot process (ie kasan_early_init) so it should not be instrumented by KASAN otherwise it bugs. Fix this by declaring phys_addr.c as non-kasan instrumentable. Signed-off-by: NAlexandre Ghiti <alexandre.ghiti@canonical.com> Fixes: 8ad8b727 (riscv: Add KASAN support) Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Alexandre Ghiti 提交于
KERN_VIRT_SIZE used to encompass the kernel mapping before it was redefined when moving the kasan mapping next to the kernel mapping to only match the maximum amount of physical memory. Then, kernel mapping addresses that go through __virt_to_phys are now declared as wrong which is not true, one can use __virt_to_phys on such addresses. Fix this by redefining the condition that matches wrong addresses. Fixes: f7ae0233 ("riscv: Move KASAN mapping next to the kernel mapping") Signed-off-by: NAlexandre Ghiti <alexandre.ghiti@canonical.com> Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Alexandre Ghiti 提交于
In order to get the pfn of a struct page* when sparsemem is enabled without vmemmap, the mem_section structures need to be initialized which happens in sparse_init. But kasan_early_init calls pfn_to_page way before sparse_init is called, which then tries to dereference a null mem_section pointer. Fix this by removing the usage of this function in kasan_early_init. Fixes: 8ad8b727 ("riscv: Add KASAN support") Signed-off-by: NAlexandre Ghiti <alexandre.ghiti@canonical.com> Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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由 Alexandre Ghiti 提交于
The KASAN region was recently moved between the linear mapping and the kernel mapping, is_linear_mapping used to check the validity of an address by using the start of the kernel mapping, which is now wrong. Fix this by using the maximum size of the physical memory. Fixes: f7ae0233 ("riscv: Move KASAN mapping next to the kernel mapping") Signed-off-by: NAlexandre Ghiti <alexandre.ghiti@canonical.com> Cc: stable@vger.kernel.org Signed-off-by: NPalmer Dabbelt <palmer@rivosinc.com>
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- 25 2月, 2022 1 次提交
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由 Arnd Bergmann 提交于
There are many different ways that access_ok() is defined across architectures, but in the end, they all just compare against the user_addr_max() value or they accept anything. Provide one definition that works for most architectures, checking against TASK_SIZE_MAX for user processes or skipping the check inside of uaccess_kernel() sections. For architectures without CONFIG_SET_FS(), this should be the fastest check, as it comes down to a single comparison of a pointer against a compile-time constant, while the architecture specific versions tend to do something more complex for historic reasons or get something wrong. Type checking for __user annotations is handled inconsistently across architectures, but this is easily simplified as well by using an inline function that takes a 'const void __user *' argument. A handful of callers need an extra __user annotation for this. Some architectures had trick to use 33-bit or 65-bit arithmetic on the addresses to calculate the overflow, however this simpler version uses fewer registers, which means it can produce better object code in the end despite needing a second (statically predicted) branch. Reviewed-by: NChristoph Hellwig <hch@lst.de> Acked-by: Mark Rutland <mark.rutland@arm.com> [arm64, asm-generic] Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org> Acked-by: NStafford Horne <shorne@gmail.com> Acked-by: NDinh Nguyen <dinguyen@kernel.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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