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  1. 01 7月, 2013 1 次提交
  3. 13 6月, 2013 2 次提交
  5. 23 5月, 2013 1 次提交
  7. 17 5月, 2013 2 次提交
  9. 09 5月, 2013 1 次提交
  11. 08 5月, 2013 3 次提交
  13. 11 4月, 2013 1 次提交
  15. 17 2月, 2013 1 次提交
  17. 01 2月, 2013 1 次提交
  19. 27 12月, 2012 1 次提交
  21. 14 12月, 2012 1 次提交
  23. 12 12月, 2012 2 次提交
  25. 26 11月, 2012 2 次提交
    • R
      MIPS: tlbex: Better debug output. · a2c763e0
      由 Ralf Baechle 提交于 
      Pgtable bits are assigned dynamically depending on processor feature and
statically based on kernel configuration.  To make sense out of the
disassembled TLB exception handlers a list of the actual assignments
used for a particular configuration and hardware setup can be very useful.

Output the actual TLB exception handlers in a format that simplifies their
post processsing from dmesg output.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a2c763e0
    • R
      MIPS: Remove R5000A. · fb2b1dba
      由 Ralf Baechle 提交于 
      From a software perspective R5000 and R5000A are the same thing which is
why the symbol CPU_R5000A never got used, so finally delete it.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      fb2b1dba
  27. 09 11月, 2012 1 次提交
    • K
      MIPS: tlbex: Fix section mismatches · f151f3b9
      由 Kevin Cernekee 提交于 
      The new functions introduced in commit 02a54177 (MIPS: tlbex: Deal with
re-definition of label) should be marked __cpuinit, to eliminate a
warning that can pop up when CONFIG_EXPORT_UASM is disabled:

      LD      arch/mips/mm/built-in.o
    WARNING: arch/mips/mm/built-in.o(.text+0x2a4c): Section mismatch in reference from the function uasm_bgezl_hazard() to the function .cpuinit.text:uasm_il_bgezl()
    The function uasm_bgezl_hazard() references
    the function __cpuinit uasm_il_bgezl().
    This is often because uasm_bgezl_hazard lacks a __cpuinit
    annotation or the annotation of uasm_il_bgezl is wrong.

    WARNING: arch/mips/mm/built-in.o(.text+0x2a68): Section mismatch in reference from the function uasm_bgezl_label() to the function .cpuinit.text:uasm_build_label()
    The function uasm_bgezl_label() references
    the function __cpuinit uasm_build_label().
    This is often because uasm_bgezl_label lacks a __cpuinit
    annotation or the annotation of uasm_build_label is wrong.

(This warning might not occur if the function was inlined.)
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4517Signed-off-by: NJohn Crispin <blogic@openwrt.org>
      f151f3b9
  29. 17 10月, 2012 2 次提交
    • R
      MIPS: R5000: Fix TLB hazard handling. · 359187d6
      由 Ralf Baechle 提交于 
      R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and
RM5271) are basically the same CPU core and all are documented to require
two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0,
c0_entrylo1 or c0_index.

So far we were only providing on cycle before / after a TLBR/TLBWI
for R5000 but 3 cycles before and 1 cycles after for the Nevadas.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      359187d6
    • R
      MIPS: tlbex: Deal with re-definition of label · 02a54177
      由 Ralf Baechle 提交于 
      The microassembler used in tlbex.c does not notice if a label is redefined
resulting in relocations against such labels silently missrelocated.
The issues exists since commit add6eb04776db4189ea89f596cbcde31b899be9d
[Synthesize TLB exception handlers at runtime.] in 2.6.10 and went unnoticed
for so long because the relocations for the affected branches got computed
to do something *almost* sensible.

The issue affects R4000, R4400, QED/IDT RM5230, RM5231, RM5260, RM5261,
RM5270 and RM5271 processors.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      02a54177
  31. 11 10月, 2012 1 次提交
  33. 14 9月, 2012 3 次提交
  35. 07 7月, 2012 1 次提交
  37. 29 3月, 2012 1 次提交
  39. 21 9月, 2011 2 次提交
  41. 26 7月, 2011 1 次提交
    • D
      MIPS: Close races in TLB modify handlers. · bf28607f
      由 David Daney 提交于 
      Page table entries are made invalid by writing a zero into the the PTE
slot in a page table.  This creates a race condition with the TLB
modify handlers when they are updating the PTE.

CPU0                              CPU1

Test for _PAGE_PRESENT
.                                 set to not _PAGE_PRESENT (zero)
Set to _PAGE_VALID

So now the page not present value (zero) is suddenly valid and user
space programs have access to physical page zero.

We close the race by putting the test for _PAGE_PRESENT and setting of
_PAGE_VALID into an atomic LL/SC section.  This requires more registers
than just K0 and K1 in the handlers, so we need to save some registers
to a save area and then restore them when we are done.

The save area is an array of cacheline aligned structures that should
not suffer cache line bouncing as they are CPU private.

[ralf@linux-mips.org: Fix !defined(CONFIG_MIPS_PGD_C0_CONTEXT) build error.]
Signed-off-by: NDavid Daney <david.daney@cavium.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2577/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      bf28607f
  43. 19 5月, 2011 1 次提交
  45. 11 5月, 2011 1 次提交
    • R
      MIPS: tlbex: Fix GCC 4.6.0 build error · 4a9040f4
      由 Ralf Baechle 提交于 
        CC      arch/mips/mm/tlbex.o
arch/mips/mm/tlbex.c: In function 'build_r4000_tlb_refill_handler':
arch/mips/mm/tlbex.c:1155:22: error: variable 'vmalloc_mode' set but not used [-Werror=unused-but-set-variable]
arch/mips/mm/tlbex.c:1154:28: error: variable 'htlb_info' set but not used [-Werror=unused-but-set-variable]
cc1: all warnings being treated as errors
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      4a9040f4
  47. 31 3月, 2011 1 次提交
  49. 15 3月, 2011 1 次提交
  51. 19 1月, 2011 3 次提交
  53. 30 10月, 2010 1 次提交
    • K
      MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code · 602977b0
      由 Kevin Cernekee 提交于 
      BMIPS processor cores are used in 50+ different chipsets spread across
5+ product lines.  In many cases the chipsets do not share the same
peripheral register layouts, the same register blocks, the same
interrupt controllers, the same memory maps, or much of anything else.

But, across radically different SoCs that share nothing more than the
same BMIPS CPU, a few things are still mostly constant:

SMP operations
Access to performance counters
DMA cache coherency quirks
Cache and memory bus configuration

So, it makes sense to treat each BMIPS processor type as a generic
"building block," rather than tying it to a specific SoC.  This makes it
easier to support a large number of BMIPS-based chipsets without
unnecessary duplication of code, and provides the infrastructure needed
to support BMIPS-proprietary features.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: NFlorian Fainelli <ffainelli@freebox.fr>
Patchwork: https://patchwork.linux-mips.org/patch/1706/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org
      602977b0
  55. 05 8月, 2010 1 次提交