- 02 9月, 2021 12 次提交
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由 Colin Ian King 提交于
There is a spelling mistake in a DC_LOG_WARNING message. Fix it. Reviewed-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
This version brings along following fixes: - FW promotion 0.0.80 - Add missing ABM register offsets - Fix in swizzle mode mapping - Emulated sink support for freesync - Improvoments in max target bpp Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Why] Swizzle mode enum for DC_SW_VAR_R_X was existing, but not mapped correctly. [How] Update mapping and conversion for DC_SW_VAR_R_X. Reviewed-by: NXiangBing Foo <XiangBing.Foo@amd.com> Reviewed-by: NMartin Leung <Martin.Leung@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com> Cc: stable@vger.kernel.org Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wyatt Wood 提交于
[Why + How] Initialize GSP1 SDP header for use in DMCUB FW. Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NWyatt Wood <wyatt.wood@amd.com> Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michael Strauss 提交于
[WHY] Clocks don't get recalculated in 0 stream/0 pipe configs, blocking S0i3 if dcfclk gets high enough [HOW] Create DCN31 copy of DCN30 bandwidth validation func which doesn't entirely skip validation in 0 pipe scenarios Override dcfclk to vlevel 0/min value during validation if pipe count is 0 Reviewed-by: NEric Yang <Eric.Yang2@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NMichael Strauss <michael.strauss@amd.com> Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Josip Pavic 提交于
[Why] Some ABM registers don't exist on DCN 3.01, so are missing from its register offset list. However, this list was copied to later versions of DCN that do have these registers. As a result, they're inaccessible from the driver on those DCN versions even though they exist. [How] Add the missing ABM register offsets to DCN 3.02+ Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NJosip Pavic <Josip.Pavic@amd.com> Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Fangzhi Zuo 提交于
1. Retrieve 128/132b link cap. 2. 128/132b link training and payload allocation. 3. UHBR10 link rate support. [squash in warning fixes - Alex] Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Fangzhi Zuo 提交于
Parse DP2 encoder caps and hpo instance from bios Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Fangzhi Zuo 提交于
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | | +--------------------+ | | v ===============|============= v +------------------+ | DIO Output Mux | +------------------+ | v +-----+ | PHY | +-----+ | PHYD32CLK[0] v +------+ | DCCG | +------+ | v SYMCLK32 Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Fangzhi Zuo 提交于
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | v +--------------------+ [squash in warning fixes - Alex] Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Fangzhi Zuo 提交于
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | v v v v +----------------------+ | HPO Stream Encoder | +----------------------+ [squash in warning fixes - Alex] Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Fangzhi Zuo 提交于
HW Blocks: +-----+ | HDA | +-----+ | | HPO ===============|============= | v | +-----+ | | APG | v +-----+ Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 9月, 2021 3 次提交
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由 Michael Strauss 提交于
[WHY] lt_settings' pointers remain uninitialized but nonzero if display fails to light up with no DPCD/EDID info populated, leading to a hang on access Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NMichael Strauss <michael.strauss@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Angus Wang 提交于
[WHY] The change has caused high idle memory clock speed and power consumption at some resolutions and frame rates for Navi10 [HOW] Reverted change "drm/amd/display: Fixed Intermittent blue screen on OLED panel" Reviewed-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NAngus Wang <angus.wang@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anson Jacob 提交于
Free memory allocated if any of the previous allocations failed. >>> CID 1487129: Resource leaks (RESOURCE_LEAK) >>> Variable "vpg" going out of scope leaks the storage it points to. Addresses-Coverity-ID: 1487129: ("Resource leaks") Reviewed-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 8月, 2021 1 次提交
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由 Jing Yangyang 提交于
./drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c:112:9-10:WARNING: return of 0/1 in function 'dcn31_is_panel_backlight_on' with return type bool ./drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c:122:9-10:WARNING: return of 0/1 in function 'dcn31_is_panel_powered_on' with return type bool Return statements in functions returning bool should use true/false instead of 1/0. Generated by: scripts/coccinelle/misc/boolreturn.cocci Reported-by: NZeal Robot <zealci@zte.com.cn> Signed-off-by: NJing Yangyang <jing.yangyang@zte.com.cn> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 27 8月, 2021 4 次提交
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由 Nicholas Kazlauskas 提交于
[Why] This is a global parameter, not a per pipe parameter and it's useful for experimenting with the prefetch schedule to be adjustable from the SOC bb. [How] Add a parameter to the SOC bb, default is the existing policy for all DCN. Fill it in when filling SOC bb parameters. Revert the policy to use MinDCFClk at the same time since that's not going to give us P-State in most cases on the spreadsheet. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
[Why & How] DML is initialized again unnecessarily after its done conditionally. Remove the duplicate initialization Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jerry (Fangzhi) Zuo 提交于
[Why] Drop hardcoded dispclk, dppclk, phyclk [How] Read the corresponding values from clock table entries already populated. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 Cc: stable@vger.kernel.org Signed-off-by: NJerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
[Why & How] The DCN3 SoC parameter num_states was calculated but not saved into the object. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 Cc: stable@vger.kernel.org Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 25 8月, 2021 2 次提交
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由 Praful Swarnakar 提交于
[Why] Recent HDMI2.0 HF1-1 V-Swing testing showed that logging deep color status helps in validation of testcase. [How] Add logging based on various color depths and pixel encoding formats. Signed-off-by: NPraful Swarnakar <Praful.Swarnakar@amd.com> Reviewed-by: NHersen Wu <hersenwu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why] A cleaner solution, only done once on boot. [How] Remove previous workaround and configure an extra vmid one time on boot Reviewed-by: NKazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 8月, 2021 1 次提交
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由 Zhan Liu 提交于
[why] dcn301_calculate_wm_and_dl() causes flickering when external monitor is connected. This issue has been fixed before by commit 0e4c0ae5 ("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"), however part of the fix was gone after commit 2cbcb78c ("Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next"). [how] Use dcn30_calculate_wm_and_dlg() instead as in the original fix. Fixes: 2cbcb78c ("Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next") Signed-off-by: NNikola Cornij <nikola.cornij@amd.com> Reviewed-by: NZhan Liu <zhan.liu@amd.com> Tested-by: NZhan Liu <zhan.liu@amd.com> Tested-by: NOliver Logush <oliver.logush@amd.com> Signed-off-by: NZhan Liu <zhan.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 17 8月, 2021 2 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - Ensure DCN save init registers after VM setup - Fix multi-display support for idle opt workqueue - Use vblank control events for PSR enable/disable - Create default dc_sink when fail reading EDID under MST Acked-by: NWayne Lin <wayne.lin@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jake Wang 提交于
[Why] DM initializes VM context after DMCUB initialization. This results in loss of DCN_VM_CONTEXT registers after z10. [How] Notify DMCUB when VM setup is complete, and have DMCUB save init registers. v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NWayne Lin <wayne.lin@amd.com> Signed-off-by: NJake Wang <haonan.wang2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 8月, 2021 1 次提交
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由 Tuo Li 提交于
The variable dc->clk_mgr is checked in: if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock) This indicates dc->clk_mgr can be NULL. However, it is dereferenced in: if (!dc->clk_mgr->funcs->get_clock) To fix this null-pointer dereference, check dc->clk_mgr and the function pointer dc->clk_mgr->funcs->get_clock earlier, and return if one of them is NULL. Reported-by: NTOTE Robot <oslab@tsinghua.edu.cn> Signed-off-by: NTuo Li <islituo@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 8月, 2021 8 次提交
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由 Randy Dunlap 提交于
Building with W=1 complains about an empty 'else' statement, so use the usual do-nothing-while-0 loop to quieten this warning. ../drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.c:113:53: warning: suggest braces around empty body in an 'else' statement [-Wempty-body] 113 | *state, retry_count); Fixes: b30eda8d ("drm/amd/display: Add ETW log to dmub_psr_get_state") Signed-off-by: NRandy Dunlap <rdunlap@infradead.org> Cc: Wyatt Wood <wyatt.wood@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
This version brings along following fixes: - Fix memory allocation in dm IRQ context to use GFP_ATOMIC - Increase timeout threshold for DMCUB reset - Clear GPINT after DMCUB has reset - Add AUX I2C tracing - Fix code commenting style - Some refactoring - Remove invalid assert for ODM + MPC case Reviewed-by: NWyatt Wood <Wyatt.Wood@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Ashley Thomas 提交于
[Why] Developers can find it useful if the driver can produce AUX traces without special equipment. [How] Add AUX tracing. Reviewed-by: NZhan Liu <zhan.liu@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NAshley Thomas <Ashley.Thomas2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Roy Chan 提交于
[How] the programming sequeune was for old asic. the correct programming sequeunce should be similar to the one used in mpc. the fix is copied from the mpc programming sequeunce. Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NRoy Chan <roy.chan@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Roy Chan 提交于
Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NRoy Chan <roy.chan@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Roy Chan 提交于
Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NRoy Chan <roy.chan@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Roy Chan 提交于
[Why] If the plane has been removed, the writeback disablement logic doesn't run [How] fix the logic order Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NRoy Chan <roy.chan@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Bernstein 提交于
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NEric Bernstein <eric.bernstein@amd.com> Cc: stable@vger.kernel.org Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 07 8月, 2021 1 次提交
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由 Colin Ian King 提交于
The variable eng_id is being initialized with a value that is never read, it is being re-assigned on the next statment. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 06 8月, 2021 5 次提交
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由 Aric Cyr 提交于
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rodrigo Siqueira 提交于
To fully isolate FPU operations in a single place, we must avoid situations where compilers spill FP values to registers due to FP enable in a specific C file. Note that even if we isolate all FPU functions in a single file and call its interface from other files, the compiler might enable the use of FPU before we call DC_FP_START. Nevertheless, it is the programmer's responsibility to invoke DC_FP_START/END in the correct place. To highlight situations where developers forgot to use the FP protection before calling the DC FPU interface functions, we introduce a helper that checks if the function is invoked under FP protection. If not, it will trigger a kernel warning. Changes cince V3: - Rebase Changes cince V2 (Christian): - Do not use this_cpu_* between get/put_cpu_ptr(). - In the kernel documentation, better describe restrictions. - Make dc_assert_fp_enabled trigger the ASSERT message. Changes since V1: - Remove fp_enable variables - Rename dc_is_fp_enabled to dc_assert_fp_enabled - Replace wrong variable type Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Reported-by: Nkernel test robot <lkp@intel.com> Signed-off-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rodrigo Siqueira 提交于
DC invokes DC_FPU_START/END in multiple parts of the code; this can create a situation where we invoke this FPU operation in a nested way or exit too early. For avoiding this situation, this commit adds a mechanism where dc_fpu_begin/end manages the access to kernel_fpu_begin/end. Change since V3: - Rebase Change since V2: - Christian: Do not use this_cpu_* between get/put_cpu_ptr(). Change since V1: - Use a better variable names - Use get_cpu_ptr and put_cpu_ptr to better balance preemption enable and disable Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Reported-by: Nkernel test robot <lkp@intel.com> Signed-off-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rodrigo Siqueira 提交于
DC invokes DC_FPU_START/END in multiple parts of the code; this can create a situation where we invoke this FPU operation in a nested way or exit too early. For avoiding this situation, this commit adds a mechanism where dc_fpu_begin/end manages the access to kernel_fpu_begin/end. Change since V3: - Christian: Move PPC64 code to dc_fpu_begin/end. Change since V2: - Christian: Do not use this_cpu_* between get/put_cpu_ptr(). Change since V1: - Use a better variable names - Use get_cpu_ptr and put_cpu_ptr to better balance preemption enable and disable Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rodrigo Siqueira 提交于
The display core files rely on FPU, which requires to be compiled with special flags. Ideally, we don't want these FPU operations spread around the DC code; nevertheless, it happens in the current source. This commit introduces a new directory inside DML for centralizing shared DCN functions that require FPU and have been used outside DML. For illustrating this process of transferring FPU functions to the DML folder, this commit moves one of the functions dcn20_populate_dml_writeback_from_context) that require FPU access to a single shared file. Notice that this is the first part of the work, and it does not fix the FPU issue yet; we still need other patches for achieving the complete FPU isolation. Changes since V3: - Jun: Instead of creating a new directory to keep the FPU code, let's make the DML folder the only part that requires FPU access. Drop fpu_operation folder. - Christian: Fix function code style. Changes since V2: - Christian: Remove unnecessary wrapper. - lkp: Add missing prototype. - Only compile the FPU operations if the DCN option is enabled. Change since V1: - Update documentation and rebase. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Reported-by: Nkernel test robot <lkp@intel.com> Signed-off-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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