1. 08 5月, 2007 11 次提交
  2. 06 5月, 2007 24 次提交
    • L
      Fix compile of tmscsim SCSI driver · 886a0768
      Linus Torvalds 提交于
      It still used the long-deprecated "pci_module_init()" interface, rather
      than the proper "pci_register_driver()" one.
      
      [ I don't have the hardware, and I doubt many do, but the fix is
        trivial and obvious, and can't be worse than not compiling ]
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      886a0768
    • M
      [TG3]: Add TG3_FLAG_SUPPORT_MSI flag. · 7544b097
      Michael Chan 提交于
      And fix up the code to always allow MSI on 5714 A2.
      
      Call tg3_find_peer() earlier because we need that information before
      we can determine whether we can set TG3_FLAG_SUPPORT_MSI or not.
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7544b097
    • F
      ide-cs: recognize 2GB CompactFlash from Transcend · aa12b284
      Fabrice Aeschbacher 提交于
      Without the following patch, the kernel does not automatically detect
      2GB CompactFlash cards from Transcend.
      Signed-off-by: NFabrice Aeschbacher <fabrice.aeschbacher@siemens.com>
      Cc: Dominik Brodowski <linux@dominikbrodowski.net>
      Acked-by: NPeter Stuge <peter@stuge.se>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      aa12b284
    • S
      hpt366: don't check enablebits for HPT36x · fdb0d72b
      Sergei Shtylyov 提交于
      HPT36x chip don't seem to have the channel enable bits, so prevent the IDE core
      from checking them...
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Michal Kepien <michal.kepien@poczta.onet.pl>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      fdb0d72b
    • B
      ide-cris: fix ->speedproc and wrong ->swdma_mask · 55e4dee3
      Bartlomiej Zolnierkiewicz 提交于
      * fix ->speedproc to set the drive speed
      
      * this driver doesn't support SWDMA so use the correct ->swdma_mask
      
      * BUG() if an unsupported mode is passed to ->speedproc
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      55e4dee3
    • B
      siimage: fix wrong ->swdma_mask · 8e60d376
      Bartlomiej Zolnierkiewicz 提交于
      This driver doesn't support SWDMA so use the correct ->swdma_mask.
      
      While at it:
      
      * no need to call config_chipset_for_pio() in config_chipset_for_dma(),
        if DMA is not available config_chipset_for_pio() will be called
        by siimage_config_drive_for_dma() and if DMA is available
        config_siimage_chipset_for_pio() will be called by siimage_tune_chipset()
      
      * remove needless config_chipset_for_pio() wrapper
      
      * bump driver version
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      8e60d376
    • B
      it821x: PIO mode setup fixes · 0e9b4e53
      Bartlomiej Zolnierkiewicz 提交于
      * limit max PIO mode to PIO4, this driver doesn't support PIO5 and attempt
        to setup PIO5 by it821x_tuneproc() could result in incorrect PIO timings
        + incorrect base clock being set for controller in the passthrough mode
      
      * move code limiting max PIO according to the pair device capabilities from
        config_it821x_chipset_for_pio() to it821x_tuneproc() so the check is also
        applied for mode change requests coming through ->tuneproc and ->speedproc
        interfaces
      
      * set device speed in it821x_tuneproc()
      
      * in it821x_tune_chipset() call it821x_tuneproc() also if the controller is
        in the smart mode (so the check for pair device max PIO is done)
      
      * rename it821x_tuneproc() to it821x_tune_pio(), then add it821x_tuneproc()
        wrapper which does the max PIO mode check;  it worked by the pure luck
        previously, pio[4] and pio_want[4] arrays were used with index == 255
        so random PIO timings and base clock were set for the controller in the
        passthrough mode, thankfully PIO timings and base clock were corrected
        later by config_it821x_chipset_for_pio() call (but it was not called for
        PIO-only devices during resume and for user requested PIO autotuning)
      
      * remove config_it821x_chipset_for_pio() call from config_chipset_for_dma()
        as the driver sets ->autotune to 1 and ->tuneproc does the proper job now
      
      * convert the last user of config_it821x_chipset_for_pio() to use
        it821x_tuneproc(drive, 255) and remove no longer needed function
      
      While at it:
      
      * fix few comments
      
      * bump driver version
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      0e9b4e53
    • B
      pdc202xx_new: enable DMA for all ATAPI devices · 247b03f8
      Bartlomiej Zolnierkiewicz 提交于
      There is no reason to limit DMA to ide_cdrom type devices.
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      247b03f8
    • B
      alim15x3: PIO fallback fix · 072cdcbb
      Bartlomiej Zolnierkiewicz 提交于
      If DMA tuning fails always set the best PIO mode.
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      072cdcbb
    • S
      aec62xx: fix PIO/DMA setup issues · 826a1b65
      Sergei Shtylyov 提交于
      Teach the driver's tuneproc() method to do PIO auto-runing properly since it
      treated 5 instead of 255 as auto-tune request, and also passed the mode limit
      of PIO5 to ide_get_best_pio_mode() despite supporting up to PIO4 only.
      
      While at it, also:
      
      - remove the driver's wrong claim about supporting SWDMA modes;
      
      - stop hooking ide_dma_timeout() method as the handler clearly doesn't fit for
        the task...
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      826a1b65
    • S
      cmd64x: use interrupt status from MRDMODE register (take 2) · 66602c83
      Sergei Shtylyov 提交于
      Fold the parts of the ide_dma_end() methods identical to __ide_dma_end() into a
      mere call to it.
      Start using faster versions of the ide_dma_end() and ide_dma_test_irq() methods
      for the PCI0646U and newer chips that have the duplicate interrupt status bits
      in the I/O mapped MRDMODE register, determing what methods to use at the driver
      load time. Do some cleanup/renaming in the "old" ide_dma_test_irq() method too.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      66602c83
    • S
      cmd64x: procfs code fixes/cleanups (take 2) · 5826b318
      Sergei Shtylyov 提交于
      Fix several issues with the driver's procfs output:
      
      - when testing if channel is enabled, the code looks at the "simplex" bits, not
        at the real enable bits -- add #define for the primary channel enable bit;
      
      - UltraDMA modes 0, 1, 3 for slave drive reported incorrectly due to using the
        master drive's clock cycle resolution bit.
      
      While at it, also perform the following cleanups:
      
      - don't print extra newline before the first controller's dump;
      
      - correct the chipset names (from CMDxxx to PCI-xxx)
      
      - don't read from the registers which aren't used for dump;
      
      - better align the table column sizes;
      
      - rework UltraDMA mode dump code;
      
      - remove PIO mode dump code that has never been finished;
      
      - remove the duplicate interrupt status (the MRDMODE register bits mirror those
        those in the CFR and ARTTIM23 registers) and fold the dump into single line;
      
      - correct the style of the ?: operators...
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      5826b318
    • S
      cmd64x: add/fix enablebits (take 2) · 7accbffd
      Sergei Shtylyov 提交于
      The IDE core looks at the wrong bit when checking if the secondary channel is
      enabled on PCI0646 -- CNTRL register bit 7 is read-ahead disable, bit 3 is the
      correct one.
      Starting with PCI0646U chip, the primary channel can also be enabled/disabled --
      so, add 'enablebits' initializers to each 'ide_pci_device_t' structure, handling
      the original PCI0646 via adding the init_setup() method and clearing the 'reg'
      field there if necessary...
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      7accbffd
    • S
      cmd64x: interrupt status fixes (take 2) · e51e2528
      Sergei Shtylyov 提交于
      The driver's ide_dma_test_irq() method was reading the MRDMODE register even on
      PCI0643/6 where it was write-only -- fix this by always reading the "backward-
      compatible" interrupt bits, renaming dma_alt_stat to irq_stat as the interrupt
      status bits are not coupled to DMA.
      In addition, wrong interrupt bit was tested/cleared for the primary channel --
      it's bit 2 in all the chip specs and the driver used bit 1... :-/
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      e51e2528
    • S
      cmd64x: fix multiword and remove single-word DMA support · 60e7a82f
      Sergei Shtylyov 提交于
      Fix the multiword DMA and drop the single-word DMA support (which nobody will
      miss, I think).  In order to do it, a number of changes was necessary:
      
      - rename program_drive_counts() to program_cycle_times(), pass to it cycle's
        total/active times instead of the clock counts, and convert them into the
        active/recovery clocks there instead of cmd64x_tune_pio() -- this causes
        quantize_timing() to also move;
      
      - contrarywise, move all the code handling the address setup timing into
        cmd64x_tune_pio(), so that setting MWDMA mode wouldn't change address setup;
      
      - remove from the speedproc() method the  bogus code pretending to set the DMA
        timings by twiddling bits in the BMIDE status register, handle setting MWDMA
        by just calling program_cycle_times(); while at it, improve the style of that
        whole switch statement;
      
      - stop fiddling with the DMA capable bits in the speedproc() method -- they do
        not enable DMA, and are properly dealt with by the dma_host_{on,off} methods;
      
      - don't set hwif->swdma_mask in the init_hwif() method anymore.
      
      In addition to those changes, do the following:
      
      - in cmd64x_tune_pio(), when writing to ARTTIM23 register preserve the interrupt
        status bit, eliminate local_irq_{save|restore}() around this code as there's
        *no* actual race with the interrupt handler, and move cmdprintk() to a more
        fitting place -- after ide_get_best_pio_mode() call;
      
      - make {arttim|drwtim}_regs arrays single-dimensional, indexed with drive->dn;
      
      - rename {setup|recovery}_counts[] into more fitting {setup|recovery}_values[];
      
      - in  the speedproc() method, get rid of the duplicate reads/writes from/to the
        UDIDETCRx registers and of the extra variable used to store the transfer mode
        value after filtering,  use another method of determining master/slave drive,
        and cleanup useless parens;
      
      - beautify cmdprintk() output here and there.
      
      While at it, remove meaningless comment about the driver being used only on
      UltraSPARC and long non-relevant RCS tag. :-)
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      60e7a82f
    • S
      sl82c105: DMA support code cleanup (take 4) · 688a87d1
      Sergei Shtylyov 提交于
      Fold the now equivalent code in the ide_dma_check() method into a mere call to
      ide_use_dma().  Make config_for_dma() return non-zero if DMA mode has been set
      and call it from the ide_dma_check() method instead of ide_dma_on().
      Defer writing the DMA timings to the chip registers until DMA is really turned
      on (and do not enable IORDY for DMA).
      Remove unneeded code from the init_hwif() method, improve its overall looks.
      Rename the dma_start(), ide_dma_check(), and ide_dma_lostirq() methods, and
      also use more proper hwif->dma_command, fix printk() and comment in the latter
      one as well.  While at it, cleanup style in several places.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      688a87d1
    • S
      sl82c105: rework PIO support (take 2) · e93df705
      Sergei Shtylyov 提交于
      Get rid of the 'pio_speed' member of 'ide_drive_t' that was only used by this
      driver by storing the PIO mode timings in the 'drive_data' instead -- this
      allows us to greatly  simplify the process of "reloading" of the chip's timing
      register and do it right in sl82c150_dma_off_quietly() and to get rid of two
      extra arguments to config_for_pio() -- which got renamed to sl82c105_tune_pio()
      and now returns a PIO mode selected, with ide_config_drive_speed() call moved
      into the tuneproc() method, now called sl82c105_tune_drive() with the code to
      set drive's 'io_32bit' and 'unmask' flags in its turn moved to its proper place
      in the init_hwif() method.
      Also, while at it, rename get_timing_sl82c105() into get_pio_timings() and get
      rid of the code in it clamping cycle counts to 32 which was both incorrect and
      never executed anyway...
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      e93df705
    • M
      [TG3]: Eliminate the TG3_FLAG_5701_REG_WRITE_BUG flag. · 98efd8a6
      Matt Carlson 提交于
      This patch removes the use of the TG3_FLAG_5701_REG_WRITE_BUG flag.
      It's logic is only used to set a function pointer and thus the
      logic can be collapsed and the flag removed.
      
      [ Comment tidy by Christoph Hellwig. -DaveM ]
      Signed-off-by: NMatt Carlson <mcarlson@broadcom.com>
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      98efd8a6
    • M
      [TG3]: Eliminate the TG3_FLAG_GOT_SERDES_FLOWCTL flag. · 5cf64b8a
      Michael Chan 提交于
      This flag does not do anything useful.
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5cf64b8a
    • M
      [TG3]: Remove reset during MAC address changes. · 986e0aeb
      Michael Chan 提交于
      The reset was added a while back so that ASF could re-init whatever
      MAC address it wanted to use after the MAC address was changed.
      Instead of resetting, we can just keep MAC address 1 unchanged during
      MAC address changes if MAC address 1 is different from MAC address 0.
      
      This fixes 2 problems:
      
      1. Bonding calls set_mac_address in contexts that cannot sleep.
      It no longer sleeps with the chip reset removed.
      
      2. When ASF shares the same MAC address as the NIC, it needs to
      always do that even when the MAC address is changed. 
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      986e0aeb
    • G
      [TG3]: WoL fixes. · a85feb8c
      Gary Zambrano 提交于
      Change TG3_FLAG_SERDES_WOL_CAP to TG3_FLAG_WOL_CAP to make it easier
      to manage WoL.  This flag is now used consistently during ethtool WoL
      setup and power setting changes.
      Signed-off-by: NGary Zambrano <zambrano@broadcom.com>
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a85feb8c
    • G
      [TG3]: Clear GPIO mask before storing. · aaf84465
      Gary Zambrano 提交于
      The GPIO settings may change during reset and so the stored values in
      tp->grc_local_ctrl should be cleared first.
      Signed-off-by: NGary Zambrano <zambrano@broadcom.com>
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      aaf84465
    • M
      [TG3]: Improve NVRAM sizing. · 989a9d23
      Matt Carlson 提交于
      This patch changes the NVRAM sizing procedure so that the driver can
      take advantage of devices with 1:1 NVRAM strapping configurations.  This
      is useful in cases where the traditional NVRAM sizing method fails.  In
      the event that the flash size cannot be determined, the largest known
      NVRAM size is used.  The patch also removes support for 5755 NVRAM
      devices that are not supported by Broadcom and adds explicit sizing for
      this device.
      Signed-off-by: NMatt Carlson <mcarlson@broadcom.com>
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      989a9d23
    • M
      [TG3]: Fix TSO bugs. · c13e3713
      Matt Carlson 提交于
      1. Remove the check for skb->len greater than MTU when doing TSO.
      When the destination has a smaller MSS than the source, a TSO packet
      may be smaller than the MTU and we still need to process it as a TSO
      packet.
      
      2. On 5705A3 devices with TSO enabled, the DMA engine can hang due to a
      hardware bug.  This patch avoids the hanging condition by reducing the
      DMA burst size.
      Signed-off-by: NMatt Carlson <mcarlson@broadcom.com>
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c13e3713
  3. 05 5月, 2007 5 次提交