1. 11 6月, 2020 1 次提交
  2. 03 6月, 2020 1 次提交
  3. 22 5月, 2020 2 次提交
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      drm/i915: Fix includes and local vars order · cac91e67
      Stanislav Lisovskiy 提交于
      Removed duplicate include and fixed comment > 80 chars.
      
      v2: Added newline after system include and between functions
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200522131843.20477-1-stanislav.lisovskiy@intel.com
      cac91e67
    • S
      drm/i915: Adjust CDCLK accordingly to our DBuf bw needs · cd191546
      Stanislav Lisovskiy 提交于
      According to BSpec max BW per slice is calculated using formula
      Max BW = CDCLK * 64. Currently when calculating min CDCLK we
      account only per plane requirements, however in order to avoid
      FIFO underruns we need to estimate accumulated BW consumed by
      all planes(ddb entries basically) residing on that particular
      DBuf slice. This will allow us to put CDCLK lower and save power
      when we don't need that much bandwidth or gain additional
      performance once plane consumption grows.
      
      v2: - Fix long line warning
          - Limited new DBuf bw checks to only gens >= 11
      
      v3: - Lets track used Dbuf bw per slice and per crtc in bw state
            (or may be in DBuf state in future), that way we don't need
            to have all crtcs in state and those only if we detect if
            are actually going to change cdclk, just same way as we
            do with other stuff, i.e intel_atomic_serialize_global_state
            and co. Just as per Ville's paradigm.
          - Made dbuf bw calculation procedure look nicer by introducing
            for_each_dbuf_slice_in_mask - we often will now need to iterate
            slices using mask.
          - According to experimental results CDCLK * 64 accounts for
            overall bandwidth across all dbufs, not per dbuf.
      
      v4: - Fixed missing const(Ville)
          - Removed spurious whitespaces(Ville)
          - Fixed local variable init(reduced scope where not needed)
          - Added some comments about data rate for planar formats
          - Changed struct intel_crtc_bw to intel_dbuf_bw
          - Moved dbuf bw calculation to intel_compute_min_cdclk(Ville)
      
      v5: - Removed unneeded macro
      
      v6: - Prevent too frequent CDCLK switching back and forth:
            Always switch to higher CDCLK when needed to prevent bandwidth
            issues, however don't switch to lower CDCLK earlier than once
            in 30 minutes in order to prevent constant modeset blinking.
            We could of course not switch back at all, however this is
            bad from power consumption point of view.
      
      v7: - Fixed to track cdclk using bw_state, modeset will be now
            triggered only when CDCLK change is really needed.
      
      v8: - Lock global state if bw_state->min_cdclk is changed.
          - Try getting bw_state only if there are crtcs in the commit
            (need to have read-locked global state)
      
      v9: - Do not do Dbuf bw check for gens < 9 - triggers WARN
            as ddb_size is 0.
      
      v10: - Lock global state for older gens as well.
      
      v11: - Define new bw_calc_min_cdclk hook, instead of using
             a condition(Manasi Navare)
      
      v12: - Fixed rebase conflict
      
      v13: - Added spaces after declarations to make checkpatch happy.
      Signed-off-by: NStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
      Reviewed-by: NManasi Navare <manasi.d.navare@intel.com>
      Signed-off-by: NManasi Navare <manasi.d.navare@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200520150058.16123-1-stanislav.lisovskiy@intel.com
      cd191546
  4. 19 5月, 2020 3 次提交
  5. 16 5月, 2020 5 次提交
  6. 15 5月, 2020 3 次提交
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    • S
      drm/i915: Restrict qgv points which don't have enough bandwidth. · 20f505f2
      Stanislav Lisovskiy 提交于
      According to BSpec 53998, we should try to
      restrict qgv points, which can't provide
      enough bandwidth for desired display configuration.
      
      Currently we are just comparing against all of
      those and take minimum(worst case).
      
      v2: Fixed wrong PCode reply mask, removed hardcoded
          values.
      
      v3: Forbid simultaneous legacy SAGV PCode requests and
          restricting qgv points. Put the actual restriction
          to commit function, added serialization(thanks to Ville)
          to prevent commit being applied out of order in case of
          nonblocking and/or nomodeset commits.
      
      v4:
          - Minor code refactoring, fixed few typos(thanks to James Ausmus)
          - Change the naming of qgv point
            masking/unmasking functions(James Ausmus).
          - Simplify the masking/unmasking operation itself,
            as we don't need to mask only single point per request(James Ausmus)
          - Reject and stick to highest bandwidth point if SAGV
            can't be enabled(BSpec)
      
      v5:
          - Add new mailbox reply codes, which seems to happen during boot
            time for TGL and indicate that QGV setting is not yet available.
      
      v6:
          - Increase number of supported QGV points to be in sync with BSpec.
      
      v7: - Rebased and resolved conflict to fix build failure.
          - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
      
      v8: - Don't report an error if we can't restrict qgv points, as SAGV
            can be disabled by BIOS, which is completely legal. So don't
            make CI panic. Instead if we detect that there is only 1 QGV
            point accessible just analyze if we can fit the required bandwidth
            requirements, but no need in restricting.
      
      v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
            simultaneously.
      
      v10: - Fix CDCLK corruption, because of global state getting serialized
             without modeset, which caused copying of non-calculated cdclk
             to be copied to dev_priv(thanks to Ville for the hint).
      
      v11: - Remove unneeded headers and spaces(Matthew Roper)
           - Remove unneeded intel_qgv_info qi struct from bw check and zero
             out the needed one(Matthew Roper)
           - Changed QGV error message to have more clear meaning(Matthew Roper)
           - Use state->modeset_set instead of any_ms(Matthew Roper)
           - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
           - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
           - Moved unrelated changes to other patch(using latency as parameter
             for plane wm calculation, moved to SAGV refactoring patch)
      
      v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
           - Remove unnecessary mask being zero check when unmasking
             qgv points as this is completely legal(Matt Roper)
           - Check if we are setting the same mask as already being set
             in hardware to prevent error from PCode.
           - Fix error message when restricting/unrestricting qgv points
             to "mask/unmask" which sounds more accurate(Matt Roper)
           - Move sagv status setting to icl_get_bw_info from atomic check
             as this should be calculated only once.(Matt Roper)
           - Edited comments for the case when we can't enable SAGV and
             use only 1 QGV point with highest bandwidth to be more
             understandable.(Matt Roper)
      
      v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
           - Changed comment for zero new_mask in qgv points masking function
             to better reflect reality(Ville Syrjälä)
           - Simplified bit mask operation in qgv points masking function
             (Ville Syrjälä)
           - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
             however this still can't be under modeset condition(Ville Syrjälä)
           - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
             (Ville Syrjälä)
           - Extracted PCode changes to separate patch.(Ville Syrjälä)
           - Now treat num_planes 0 same as 1 to avoid confusion and
             returning max_bw as 0, which would prevent choosing QGV
             point having max bandwidth in case if SAGV is not allowed,
             as per BSpec(Ville Syrjälä)
           - Do the actual qgv_points_mask swap in the same place as
             all other global state parts like cdclk are swapped.
             In the next patch, this all will be moved to bw state as
             global state, once new global state patch series from Ville
             lands
      
      v14: - Now using global state to serialize access to qgv points
           - Added global state locking back, otherwise we seem to read
             bw state in a wrong way.
      
      v15: - Added TODO comment for near atomic global state locking in
             bw code.
      
      v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
             with Jani Nikula.
           - Take bw_state_changed flag into use.
      
      v17: - Moved qgv point related manipulations next to SAGV code, as
             those are semantically related(Ville Syrjälä)
           - Renamed those into intel_sagv_(pre)|(post)_plane_update
             (Ville Syrjälä)
      
      v18: - Move sagv related calls from commit tail into
             intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)
      
      v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
             for commit tail stage.
      
      v20: - Return max bandwidth for 0 planes(Ville)
           - Constify old_bw_state in bw_atomic_check(Ville)
           - Removed some debugs(Ville)
           - Added data rate to debug print when no QGV points(Ville)
           - Removed some comments(Ville)
      
      v21, v22, v23: - Fixed rebase conflict
      
      v24: - Changed PCode mask to use ICL_ prefix
      v25: - Resolved rebase conflict
      
      v26: - Removed redundant NULL checks(Ville)
           - Removed redundant error prints(Ville)
      
      v27: - Use device specific drm_err(Ville)
           - Fixed parenthesis ident reported by checkpatch
             Line over 100 warns to be fixed together with
             existing code style.
      Signed-off-by: NStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@intel.com>
      Cc: James Ausmus <james.ausmus@intel.com>
      [vsyrjala: Drop duplicate intel_sagv_{pre,post}_plane_update() prototypes
                 and drop unused NUM_SAGV_POINTS define]
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-3-stanislav.lisovskiy@intel.com
      20f505f2
    • S
      drm/i915: Add TGL+ SAGV support · 7241c57d
      Stanislav Lisovskiy 提交于
      Starting from TGL we need to have a separate wm0
      values for SAGV and non-SAGV which affects
      how calculations are done.
      
      v2: Remove long lines
      v3: Removed COLOR_PLANE enum references
      v4, v5, v6: Fixed rebase conflict
      v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
          - Removed sagv_uv_wm0(Ville)
          - can_sagv->use_sagv_wm(Ville)
      
      v8: - Moved tgl_crtc_can_enable_sagv function up(Ville)
          - Changed comment regarding pipe_wm usage(Ville)
          - Call intel_can_enable_sagv and tgl_compute_sagv_wm only
            for Gen12(Ville)
          - Some sagv debugs removed(Ville)
          - skl_print_wm_changes improvements(Ville)
          - Do assignment instead of memcpy in
            skl_pipe_wm_get_hw_state(Ville)
      
      v9: - Removed can_sagv variable(Ville)
          - Removed spurious line(Ville)
          - Changed u32 to unsigned int as agreed(Ville)
          - Assign sagv only for gen12 in
            skl_pipe_wm_get_hw_state(Ville)
      Signed-off-by: NStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
      [vsyrjala: Remove the dead 'return false' from intel_crtc_can_enable_sagv()]
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-2-stanislav.lisovskiy@intel.com
      7241c57d
  7. 13 5月, 2020 3 次提交
  8. 11 5月, 2020 1 次提交
  9. 04 5月, 2020 4 次提交
  10. 29 4月, 2020 1 次提交
  11. 21 4月, 2020 1 次提交
  12. 18 4月, 2020 2 次提交
  13. 15 4月, 2020 1 次提交
  14. 05 3月, 2020 4 次提交
  15. 04 3月, 2020 2 次提交
  16. 03 3月, 2020 1 次提交
  17. 02 3月, 2020 4 次提交
  18. 29 2月, 2020 1 次提交