DC was using compile time initialization of register addresses using
SR_* macros and their variants. These have been converted to use runtime
initialization.

The REG_STRUCT macro is a definition that is added to SR_* macros.
During initialization, this must be defined before SR_* macros are
invoked, which are in turn invoked through various IP initialization macros.
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Retrying on receiving a NACK can result in long overall EDID read times
in some cases.

[How]
Retry only on DEFER and return immediately on NACK.
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NIlya Bakoulin <Ilya.Bakoulin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Reprogramming the stream despite no changes in ODM combine mode.
Reprogramming the stream would cause intermittent black screen on
display which could only be recovered through enable/disable sequence.

[HOW]
Fixed bug where we detected a change in ODM combine mode despite ODM
combine mode being disabled. Also removed code which required stream to
be reprogrammed once a change in ODM combine mode was noticed. Lastly we
do not support dynamic ODM switching for HDMI TMDS and FRL on DCN32,
therefore we never want to change its ODM policy.
Reviewed-by: NSamson Tam <Samson.Tam@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NSaaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
odm 2:1 policy is splitting the pipes in 4k144.
then in subvp code, we merge the pipes. but since the
 configuration is unsupported, we keep the pipes split

[How]
for unsupported subvp configuration, redo the dml and
 pipe split calls
Reviewed-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NSamson Tam <samson.tam@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
RV2 do not change pipe split policy in the
minimal pipe split transition state.
This will unblock mode support on some
parts that limit to DPM0 for power reason.

[How]
Do not change pipe split policy in the
minimal pipe split transition state to
allow 4k multi display configs to be
supported at DPM0.
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NDerek Lai <Derek.Lai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This verion brings along following fixes:
-Add scaling factor for SubVP
-Modify stop_dbg_mode return value
-Add gfx_off members and document
-Add GFXOFF function for vangogh
-Add GFXOFF stats to debug
-Fix codestyle problems
-Fix overflow on MIN_I64
-Fix Unneeded semicolon
-Fix comment typo
-Remove useless condition in amdgpu_job_stop_all_jobs_on_sched()
-Add decoder_iv_ts helper for ih_v6
-Add chip version to DCN32
-Avoid doing vm_init multiple time
-Modify size calculation in MALL
-Fix DSC for phantom pipes
-Update clock table policy for DCN314
-Modify header inclusion pattern
-Fix plug/unplug external monitor will playback MPO video
-Add debug parameter to retain default clock table
-Increase tlb flush timeout for sriov
-Fix compare intergers of different widths
-Add reserved dc_log_type
-Fix pixel clock programming
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- For SubVP add scaling factor to allow firmware to calculate
 accurate line to start programming
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Skip set_topology_info as xgmi TA will now block it
and host needs to program it.
Signed-off-by: NVignesh Chander <Vignesh.Chander@amd.com>
Reviewed-By : Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For some ASICs, like GFX IP v11.0.1, only have one SDMA instance,
so not need to configure SDMA1_RLC_CGCG_CTRL for this case.
Signed-off-by: NTim Huang <tim.huang@amd.com>
Reviewed-by: NYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Removes DEFINEs that should have been removed after they were
introduced to ObjectID.h by the commit abea57d7
("drm/amdgpu: Add BRACKET_LAYOUT_ENUMs to ObjectID.h")
Signed-off-by: NTales Aparecida <tales.aparecida@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DCN314 supports PCON.

[How]
Explicitly enable it in dcn314 resources.
Signed-off-by: NRoman Li <roman.li@amd.com>
Reviewed-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable AMD_CG_SUPPORT_BIF_MGCG and AMD_CG_SUPPORT_BIF_LS support.
Signed-off-by: NTim Huang <tim.huang@amd.com>
Reviewed-by: NYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add BIF Clock Gating MGCG and LS support for NBIO IP v7.7.0.
Signed-off-by: NTim Huang <tim.huang@amd.com>
Reviewed-by: NYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.
Signed-off-by: NTim Huang <tim.huang@amd.com>
Reviewed-by: NYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Although radeon card fence and wait for gpu to finish processing current batch rings,
there is still a corner case that radeon lockup work queue may not be fully flushed,
and meanwhile the radeon_suspend_kms() function has called pci_set_power_state() to
put device in D3hot state.
Per PCI spec rev 4.0 on 5.3.1.4.1 D3hot State.
> Configuration and Message requests are the only TLPs accepted by a Function in
> the D3hot state. All other received Requests must be handled as Unsupported Requests,
> and all received Completions may optionally be handled as Unexpected Completions.
This issue will happen in following logs:
Unable to handle kernel paging request at virtual address 00008800e0008010
CPU 0 kworker/0:3(131): Oops 0
pc = [<ffffffff811bea5c>]  ra = [<ffffffff81240844>]  ps = 0000 Tainted: G        W
pc is at si_gpu_check_soft_reset+0x3c/0x240
ra is at si_dma_is_lockup+0x34/0xd0
v0 = 0000000000000000  t0 = fff08800e0008010  t1 = 0000000000010000
t2 = 0000000000008010  t3 = fff00007e3c00000  t4 = fff00007e3c00258
t5 = 000000000000ffff  t6 = 0000000000000001  t7 = fff00007ef078000
s0 = fff00007e3c016e8  s1 = fff00007e3c00000  s2 = fff00007e3c00018
s3 = fff00007e3c00000  s4 = fff00007fff59d80  s5 = 0000000000000000
s6 = fff00007ef07bd98
a0 = fff00007e3c00000  a1 = fff00007e3c016e8  a2 = 0000000000000008
a3 = 0000000000000001  a4 = 8f5c28f5c28f5c29  a5 = ffffffff810f4338
t8 = 0000000000000275  t9 = ffffffff809b66f8  t10 = ff6769c5d964b800
t11= 000000000000b886  pv = ffffffff811bea20  at = 0000000000000000
gp = ffffffff81d89690  sp = 00000000aa814126
Disabling lock debugging due to kernel taint
Trace:
[<ffffffff81240844>] si_dma_is_lockup+0x34/0xd0
[<ffffffff81119610>] radeon_fence_check_lockup+0xd0/0x290
[<ffffffff80977010>] process_one_work+0x280/0x550
[<ffffffff80977350>] worker_thread+0x70/0x7c0
[<ffffffff80977410>] worker_thread+0x130/0x7c0
[<ffffffff80982040>] kthread+0x200/0x210
[<ffffffff809772e0>] worker_thread+0x0/0x7c0
[<ffffffff80981f8c>] kthread+0x14c/0x210
[<ffffffff80911658>] ret_from_kernel_thread+0x18/0x20
[<ffffffff80981e40>] kthread+0x0/0x210
 Code: ad3e0008  43f0074a  ad7e0018  ad9e0020  8c3001e8  40230101
 <88210000> 4821ed21
So force lockup work queue flush to fix this problem.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NZhenneng Li <lizhenneng@kylinos.cn>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

dml_wrapper* files were removed in commit 01b537ee
("drm/amd/display: Remove unused code"), as they are not used anywhere.
However, the header file wasn't removed, so remove the header as well.
Signed-off-by: NMagali Lemes <magalilemes00@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The file amdgpu_dm_plane.c missed the header amdgpu_dm_plane.h, which
resulted on the following warning:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1046:5:
warning: no previous prototype for 'fill_dc_scaling_info'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1222:6:
warning: no previous prototype for 'handle_cursor_update'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:152:6:
warning: no previous prototype for 'modifier_has_dcc'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1576:5:
warning: no previous prototype for 'amdgpu_dm_plane_init'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:157:10:
warning: no previous prototype for 'modifier_gfx9_swizzle_mode'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:752:5:
warning: no previous prototype for 'fill_plane_buffer_attributes'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:83:31:
warning: no previous prototype for 'amd_get_format_info'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:88:6:
warning: no previous prototype for 'fill_blending_from_plane_state'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:992:5:
warning: no previous prototype for 'dm_plane_helper_check_state'
[-Wmissing-prototypes]

Therefore, include the missing header on the file and turn global functions
that are not used outside of the file into static functions.

Fixes: 5d945cbc ("drm/amd/display: Create a file dedicated to planes")
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NMaíra Canal <mairacanal@riseup.net>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Semicolon is not required after curly braces.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1918Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Addresses the following warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3596:6: error: stack frame size (2092) exceeds limit (2048) in 'dml30_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than]
void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
     ^

UseMinimumDCFCLK() is eating away at
dml30_ModeSupportAndSystemConfigurationFull()'s stack space, so use a
pointer to struct vba_vars_st instead of passing lots of large arrays
as parameters by value.
Signed-off-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The additional call is caused by merge conflict
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Nshaoyunl <shaoyun.liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No need to set up rb when no gfx rings.
Signed-off-by: NCandice Li <candice.li@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Only amdgpu_get_xgmi_hive but no amdgpu_put_xgmi_hive
which will leak the hive reference.
Signed-off-by: NYiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

V1:
The amdgpu_xgmi_remove_device function will send unload command
to psp through psp ring to terminate xgmi, but psp ring has been
destroyed in psp_hw_fini.

V2:
1. Change the commit title.
2. Restore amdgpu_xgmi_remove_device to its original calling location.
   Move psp_xgmi_terminate call from amdgpu_xgmi_remove_device to
   psp_hw_fini.
Signed-off-by: NYiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable GFXOFF allow control when set the GFX power gating.
Signed-off-by: NTim Huang <tim.huang@amd.com>
Reviewed-by: NYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add comments to document gfx_off related members of struct amdgpu_gfx.
Signed-off-by: NAndré Almeida <andrealmeid@igalia.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add documentation explaining those two new files.

While here, add a note about the value type.
Signed-off-by: NAndré Almeida <andrealmeid@igalia.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Implement functions to get and set GFXOFF's entry count and residency
for vangogh.
Signed-off-by: NAndré Almeida <andrealmeid@igalia.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add debugfs interface to log GFXOFF statistics:

- Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the
  time of query since system power-up

- Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop.
  Read it to get average GFXOFF residency % multiplied by 100
  during the last logging interval.

Both features are designed to be keep the values persistent between
suspends.
Signed-off-by: NAndré Almeida <andrealmeid@igalia.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes five checkpatch warnings:

CHECK: Please don't use multiple blank lines
+
+

ERROR: Macros with complex values should be enclosed in parentheses
+#define MAX_I64 \
+       (int64_t)((1ULL << 63) - 1)

WARNING: Missing a blank line after declarations
+       struct bw_fixed res;
+       ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32);

ERROR: that open brace { should be on the previous line
+               do
+               {

ERROR: that open brace { should be on the previous line
+                       if (remainder >= arg2_value)
+                       {
Signed-off-by: NTales Aparecida <tales.aparecida@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The definition of MIN_I64 in bw_fixed.c can cause gcc to whinge about
integer overflow, because it is treated as a positive value, which is
then negated. The temporary positive value is not necessarily
representable.

This causes the following warning:
../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.c:30:19:
warning: integer overflow in expression ‘-9223372036854775808’ of type
‘long long int’ results in ‘-9223372036854775808’ [-Woverflow]
  30 |         (int64_t)(-(1LL << 63))
     |                   ^

Writing out (-MAX_I64 - 1) works instead.
Signed-off-by: NDavid Gow <davidgow@google.com>
Signed-off-by: NTales Aparecida <tales.aparecida@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There is no semicolon after '}' in line 510.
Signed-off-by: Nmin tang <tangmin@cdjrlc.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The double `aligned' is duplicated in line 1070, remove one.
Signed-off-by: Nmin tang <tangmin@cdjrlc.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We have some old code associated with DML, which we had plans to use,
but at some point, we just moved away from it. This commit removes the
dml_wrapper* files since they are not used anymore.
Reported-by: NMagali Lemes <magalilemes00@gmail.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The second jump table is required on live migration or mulitple VF
configuration on Aldebaran. With this implemented, the first level
jump table(hw used) will be same, mec fw internal will use the
second level jump table jump to the real functionality implementation.
so the different VF can load different version of MEC as long as
they support sjt
Signed-off-by: Nshaoyunl <shaoyun.liu@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Currently, we are using soc._clock_tmp[] to temporarily store and modify
data from soc.clock_limits[] before copying it back into
soc.clock_limits[] (because modifying data directly in
soc.clock_limits[] causes unintended behavior). However, this approach
has a number of downsides, such as:

	1. struct _vcs_dpi_soc_bounding_box_st's creation/destruction
	   aren't well defined (which could mean more unintended
	   behavior).
	2. Throwing "temp" varibles in structs everywhere doesn't make
	   for a particularly readable codebase.

For these reasons, we should get rid of soc._clock_tmp[] by defining a
struct scratch within struct dc that, contains within it all of the
temporary variables (including _clock_tmp[]) such that it is obvious how
they are intended to be used.
Co-authored-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Currently, we only attempt to setup DSC at the virtual DPCD port,
however many modern displays come with DSC support and MST hubs can now
support DSC pass-through. So, to more optimally make use of the
available bandwidth, use DSC pass-through when possible by adding DSC
pass-through enablement support into the DSC enable sequence.
Signed-off-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add a mode validation routine for DSC pass-through. Both the link from
source to hub, and the link from hub to monitor are checked, according
to the current link training result and full pbn returned by enum path
resource sideband message.

Pick up the minimum value as the bandwidth bottleneck for the end to
end link bandwidth constraint, and check if the maximum DSC decompression
bandwidth can fit.

v2: squash in DSC CONFIG_DRM_AMD_DC_DCN compilation fix (Hamza)
Co-authored-by: NFangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Currently, there is no way to identify if DSC pass-through can be
enabled and what aux DSC pass-through requests ought to be sent to. So,
add a variable to struct drm_dp_mst_port that keeps track of the
aforementioned information.
Reviewed-by: NLyude Paul <lyude@redhat.com>
Signed-off-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

AMD GPU display manager (DM) maps DRM pixel blend modes (None,
Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
options. Describe relevant elements and how to set and test them to get
the expected DRM blend mode on DCN hw.

v2:
- add ref tag (Tales)
Signed-off-by: NMelissa Wen <mwen@igalia.com>
Reviewed-by: NTales Aparecida <tales.aparecida@gmail.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Describe structs and enums used to set blend mode properties to MPC
blocks. Some pieces of information are already available as code
comments, and were just formatted. Others were collected and summarised
from discussions on AMD issue tracker[1][2].

[1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734
[2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769

v2:
- fix typos (Tales)
- add MPCC to MPC entry in the glossary
Signed-off-by: NMelissa Wen <mwen@igalia.com>
Reviewed-by: NTales Aparecida <tales.aparecida@gmail.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>