The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the IPQ806x family of SoCs.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch fixes a possible timeout in poll loop without actually
checking the register before return. In theory the there is a possibility
of loop being scheduled after a long lock/delay, which would then force
the loop to exit without actually checking the register.
Reported-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

In case of multi-phy PHY providers, each PHY should be modeled as a sub
node of the PHY provider. Then each PHY will have a different node pointer
(node pointer of sub node) than that of PHY provider. Added this provision
in the PHY core.
Also fixed all drivers to use the updated API.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NLee Jones <lee.jones@linaro.org>

Fixed of_phy_provider_lookup to return 'phy_provider' if _of_phy_get
passes the node pointer of the sub-node of phy provider node. This is
needed when phy provider implements multiple PHYs and each PHY is
modelled as the sub-node of PHY provider device node.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NLee Jones <lee.jones@linaro.org>

The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: NAntoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.

The mode selection can let us think this PHY can be configured to fit
other purposes. But there are reasons to think the SATA mode will be
the only one usable: the PHY registers are only accessible indirectly
through two registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: NAntoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu.
Depend on MACH_KIRKWOOD, which will be set when these SoCs are built
as part of mach-mvebv.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds binding spec for Qualcomm AP8064 SATA PHY.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: NKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.

This patch is a forward port from Qualcomm's v3.4 andriod kernel.

Tested on IFC6410 board.

CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
Tested-by: NKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

USB DWC3 driver on Exynos platform does not work without its
corresponding phy driver. Hence make the PHY driver depend on
Exynos DWC3 driver and default it to yes to make things easier
for the end user.
Signed-off-by: NSachin Kamat <sachin.kamat@samsung.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Tested-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and
USB gadget controller supported by the DWC2 gadget driver, make it
depend on them and default to ARCH_EXYNOS as they are meant for
Exynos platforms. Also, make the sub-drivers silent options enabling
them based on the SoC platforms that they are meant to work with. This
will make life easier for end users who do not have any way knowing the
dependencies.
Signed-off-by: NSachin Kamat <sachin.kamat@samsung.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Tested-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

phy-supply is a phandle to the regulator that provides power to the
PHY. This regulator is managed during the PHY power on/off sequence
by the phy core driver.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Some PHYs can be powered by an external power regulator.
e.g. USB_HS PHY on DRA7 SoC. Make the PHY core support a
power regulator.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds support for Exynos3250 SoC to Exynos2USB PHY driver.
Although Exynos3250 has only one device phy interface, the register
layout and all operations that are required to get it enabled are almost
same as on Exynos4x12. The only different is one more register
(REFCLKSEL) which need to be set and lack of MODE SWITCH register.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc.
Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add necessary binding documentation SATA PHY on Hisilicon hix5hd2 soc.
Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRoger Quadros <rogerq@ti.com>

PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRoger Quadros <rogerq@ti.com>

The Exynos4412 USB 2.0 PHY hardware differs from the description provided
in the documentation. Some register bits have different function. This
patch fixes the defines of register bits and changes the way how phys are
powered on and off.
Signed-off-by: NKamil Debski <k.debski@samsung.com>
Tested-by: NDaniel Drake <drake@endlessm.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Make local functions static, because these are used only in this
file.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

PTR_ERR_OR_ZERO simplifies the code.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

PTR_ERR_OR_ZERO simplifies the code.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

PTR_ERR_OR_ZERO simplifies the code.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Cc: Jingoo Han <jg1.han@samsung.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This provides the shared header file which will be reference from both
the MiPHY365x driver and its associated Device Tree node(s).

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Pull ext4 bugfixes from Ted Ts'o:
 "More bug fixes for ext4 -- most importantly, a fix for a bug
  introduced in 3.15 that can end up triggering a file system corruption
  error after a journal replay.

  It shouldn't lead to any actual data corruption, but it is scary and
  can force file systems to be remounted read-only, etc"

* tag 'ext4_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4:
  ext4: fix potential null pointer dereference in ext4_free_inode
  ext4: fix a potential deadlock in __ext4_es_shrink()
  ext4: revert commit which was causing fs corruption after journal replays
  ext4: disable synchronous transaction batching if max_batch_time==0
  ext4: clarify ext4_error message in ext4_mb_generate_buddy_error()
  ext4: clarify error count warning messages
  ext4: fix unjournalled bg descriptor while initializing inode bitmap

Pull clock driver fixes from Mike Turquette:
 "This batch of fixes is for a handful of clock drivers from Allwinner,
  Samsung, ST & TI.  Most of them are of the "this hardware won't work
  without this fix" variety, including patches that fix platforms that
  did not boot under certain configurations.  Other fixes are the result
  of changes to the clock core introduced in 3.15 that had subtle
  impacts on the clock drivers.

  There are no fixes to the clock framework core in this pull request"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk: spear3xx: Set proper clock parent of uart1/2
  clk: spear3xx: Use proper control register offset
  clk: qcom: HDMI source sel is 3 not 2
  clk: sunxi: fix devm_ioremap_resource error detection code
  clk: s2mps11: Fix double free corruption during driver unbind
  clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
  clk: exynos5420: Remove aclk66_peric from the clock tree description
  clk/exynos5250: fix bit number for tv sysmmu clock
  clk: s3c64xx: Hookup SPI clocks correctly
  clk: samsung: exynos4: Remove SRC_MASK_ISP gates
  clk: samsung: add more aliases for s3c24xx
  clk: samsung: fix several typos to fix boot on s3c2410
  clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock
  clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
  clk: ti: dra7: return error code in failure case
  clk: ti: apll: not allocating enough data

Pull ARM SoC fixes from Olof Johansson:
 "This week's arm-soc fixes:

   - Another set of OMAP fixes
     * Clock fixes
     * Restart handling
     * PHY regulators
     * SATA hwmod data for DRA7
     + Some trivial fixes and removal of a bit of dead code
   - Exynos fixes
     * A bunch of clock fixes
     * Some SMP fixes
     * Exynos multi-core timer: register as clocksource and fix ftrace.
     + a few other minor fixes

  There's also a couple more patches, and at91 fix for USB caused by
  common clock conversion, and more MAINTAINERS entries for shmobile.

  We're definitely switching to only regression fixes from here on out,
  we've been a little less strict than usual up until now"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  ARM: at91: at91sam9x5: add clocks for usb device
  ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250
  ARM: dts: Add clock property for mfc_pd in exynos5420
  clk: exynos5420: Add IDs for clocks used in PD mfc
  ARM: EXYNOS: Add support for clock handling in power domain
  ARM: OMAP2+: Remove non working OMAP HDMI audio initialization
  ARM: imx: fix shared gate clock
  ARM: dts: Update the parent for Audss clocks in Exynos5420
  ARM: EXYNOS: Update secondary boot addr for secure mode
  ARM: dts: Fix TI CPSW Phy mode selection on IGEP COM AQUILA.
  ARM: dts: am335x-evmsk: Enable the McASP FIFO for audio
  ARM: dts: am335x-evm: Enable the McASP FIFO for audio
  ARM: OMAP2+: Make GPMC skip disabled devices
  ARM: OMAP2+: create dsp device only on OMAP3 SoCs
  ARM: dts: dra7-evm: Make VDDA_1V8_PHY supply always on
  ARM: DRA7/AM43XX: fix header definition for omap44xx_restart
  ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow
  ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
  ARM: DRA7: hwmod: Fixup SATA hwmod
  ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driver
  ...

Pull ARM fixes from Russell King:
 "Another round of fixes for ARM:
   - a set of kprobes fixes from Jon Medhurst
   - fix the revision checking for the L2 cache which wasn't noticed to
     have been broken"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: l2c: fix revision checking
  ARM: kprobes: Fix test code compilation errors for ARMv4 targets
  ARM: kprobes: Disallow instructions with PC and register specified shift
  ARM: kprobes: Prevent known test failures stopping other tests running

Pull m68k fixes from Geert Uytterhoeven:
 "Summary:
  - Fix for a boot regression introduced in v3.16-rc1,
  - Fix for a build issue in -next"

Christoph Hellwig questioned why mach_random_get_entropy should be
exported to modules, and Geert explains that random_get_entropy() is
called by at least the crypto layer and ends up using it on m68k.  On
most other architectures it just uses get_cycles() (which is typically
inlined and doesn't need exporting),

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k:
  m68k: Export mach_random_get_entropy to modules
  m68k: Fix boot regression on machines with RAM at non-zero

Pull parisc fixes from Helge Deller:
 "The major patch in here is one which fixes the fanotify_mark() syscall
  in the compat layer of the 64bit parisc kernel.  It went unnoticed so
  long, because the calling syntax when using a 64bit parameter in a
  32bit syscall is quite complex and even worse, it may be even
  different if you call syscall() or the glibc wrapper.  This patch
  makes the kernel accept the calling convention when called by the
  glibc wrapper.

  The other two patches are trivial and remove unused headers, #includes
  and adds the serial ports of the fastest C8000 workstation to the
  parisc-kernel internal hardware database"

* 'parisc-3.16-5' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: drop unused defines and header includes
  parisc: fix fanotify_mark() syscall on 32bit compat kernel
  parisc: add serial ports of C8000/1GHz machine to hardware database

The uarts only work when the parent is ras_ahb_clk. The stale 3.5
based ST tree does this in the board file.

Add it to the clk init function. Not pretty, but the mess there is
amazing anyway.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62 (SPEAr: Switch to common clock framework).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NHelge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # 3.13+

On parisc we can not use the existing compat implementation for fanotify_mark()
because for the 64bit mask parameter the higher and lower 32bits are ordered
differently than what the compat function expects from big endian
architectures.

Specifically:
It finally turned out, that on hppa we end up with different assignments
of parameters to kernel arguments depending on if we call the glibc
wrapper function
 int fanotify_mark (int __fanotify_fd, unsigned int __flags,
                    uint64_t __mask, int __dfd, const char *__pathname);
or directly calling the syscall manually
 syscall(__NR_fanotify_mark, ...)

Reason is, that the syscall() function is implemented as C-function and
because we now have the sysno as first parameter in front of the other
parameters the compiler will unexpectedly add an empty paramenter in
front of the u64 value to ensure the correct calling alignment for 64bit
values.
This means, on hppa you can't simply use syscall() to call the kernel
fanotify_mark() function directly, but you have to use the glibc
function instead.

This patch fixes the kernel in the hppa-arch specifc coding to adjust
the parameters in a way as if userspace calls the glibc wrapper function
fanotify_mark().
Signed-off-by: NHelge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # 3.13+

Signed-off-by: NHelge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # 3.13+

Pull slave-dmaengine fixes from Vinod Koul:
 "We have two small fixes.  First one from Daniel to handle 0-length
  packets for usb cppi dma.  Second by Russell for imx-sdam cyclic
  residue reporting"

* 'fixes' of git://git.infradead.org/users/vkoul/slave-dma:
  Update imx-sdma cyclic handling to report residue
  dma: cppi41: handle 0-length packets

Merge tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes

Merge "Samsung fixes-3 for 3.16" from Kukjin Kim:

Samsung fixes-3 for v3.16
- update the parent for Auudss clock because kernel will be hang
  during late boot if the parent clock is disabled in bootloader.
- enable clk handing in power domain because while power domain
  on/off, its regarding clock source will be reset and it causes
  a problem so need to handle it.
- add mux clocks to be used by power domain for exynos5420-mfc
  during power domain on/off and property in device tree also.
- register cpuidle only for exynos4210 and exynos5250 because a
  system failure will be happened on other exynos SoCs.

* tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250
  ARM: dts: Add clock property for mfc_pd in exynos5420
  clk: exynos5420: Add IDs for clocks used in PD mfc
  ARM: EXYNOS: Add support for clock handling in power domain
  ARM: dts: Update the parent for Audss clocks in Exynos5420
Signed-off-by: NOlof Johansson <olof@lixom.net>