The Kconfig options selected by ARCH_TEGRA_*_SOC were recently sorted.
Update the newly added ARCH_TEGRA_114_SOC's select statements to match.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

CONFIG_ARCH_TEGRA_114_SOC doesn't currently enable gpiolib, which causes
numerous build problems building a Tegra kernel with only Tegra114
enabled, and not Tegra20 or Tegra30. Enable ARCH_REQUIRE_GPIOLIB to
solve this. However, all Tegra will use gpiolib, so select this option
from ARCH_TEGRA rather than each individual ARCH_TEGRA_*_SOC, to
prevent this problem for any future chips.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch fixes the build error when ARCH_TEGRA_114_SOC is enabled
and ARCH_TEGRA_3x_SOC is disabled.

This provides Tegra114 with its own tegra114_init_early() instead of
making use of tegra30_init_early() so that T114 build doesn't depend
on T3x anymore.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Fix build error in board-dt-tegra114.c(next-20130204)
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Reported-by: Sami Liedes<sliedes@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Based on two separate cleanup branches, it's now empty and can be removed.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Cc: Stephen Warren <swarren@wwwdotorg.org>

Select PINCTRL and PINCTRL_TEGRA114 for enabling Tegra114 pincontrol
driver for Tegra114 SoC.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add new Tegra 114 SoC support.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add tegra_chip_id TEGRA114 0x35
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state then go into "powered-down"
idle mode together. The driver can just assume the MPCore come into
"powered-down" mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).

The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting CPU0 in the same state.
When the CPU0 requests powered-down state, it attempts to put the secondary
CPU into reset to prevent it from waking up. Then power down both CPUs
together and power off the cpu rail.

Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NColin Cross <ccross@android.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20 had a limition to
power down both CPU cores. The secondary CPU must waits for CPU0 in
powered-down state too. If the secondary CPU be woken up before CPU0
entering powered-down state, then it needs to restore its CPU states
and waits for next chance.

Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".

Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
include the power of GIC. That caused the SGI (Software Generated
Interrupt) been lost. Because the SGI can't wake up the CPU that in
the "powered-down" CPU idle mode. We need to check if there is any
pending SGI when go into "powered-down" CPU idle mode. This is important
especially when applying the coupled cpuidle framework into "power-down"
cpuidle dirver. Because the coupled cpuidle framework may have the
chance that misses IPI_SINGLE_FUNC handling sometimes.

For the PPI or SPI, something like the legacy peripheral interrupt. It
still can be maintained by Tegra legacy interrupt controller. If there
is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
CPU can be woken up immediately. So we don't need to take care the same
situation for PPI or SPI.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

USB register base address and sizes defined in iomap.h
are not used in any files other than board-dt-tegra20.c.
Hence removed those defines from header file and using
the absolute values in board files.
Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Remove AUXDATA as clocks are initialized from device node.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Remove AUXDATA as clock are initialized from device node.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Remove all legacy clock code from mach-tegra.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra.
Move the tegra_cpu_car_ops to include/linux/clk/tegra.h.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add function to read chip id from APB MISC registers. This function
will also get called from clock driver to flush write operations on
apb bus.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The "sleep.S" file has many functions that be shared by different module
currently. Not just for CPU idle driver. Make it build as default now.
Reported-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
[swarren: add sleep.o to separate line so each line only contains 1 file]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

It would rather to use the API of time_to_jiffies than a constant number
of jiffies for the wait time of CPU power up.

Based on the work by:
Sang-Hun Lee <sanlee@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The reset handler code is used for either UP or SMP. To make Tegra device
can compile for UP. It needs to be moved to another file that is not SMP
only. This is because the reset handler also be needed by CPU idle
"powered-down" mode. So we also need to put the reset handler init function
in non-SMP only and init them always.

And currently the implementation of the reset handler to know which CPU is
OK to bring up was identital with "cpu_present_mask". But the
"cpu_present_mask" did not initialize yet when the reset handler init
function was moved to init early function. We use the "cpu_possible_mask"
to replace "cpu_present_mask". Then it can work on both UP and SMP case.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
[swarren: dropped the move of v7_invalidate_l1() from one file to another,
to avoid conflicts with Pavel's cleanup of this function, adjust Makefile
so each line only contains 1 file.]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

SCU based detection only works with Cortex-A9 MP and it doesn't
support ones with multiple clusters. The only way to detect number of
CPU core correctly is with DT /cpu node.

Tegra SoCs decided to use DT detection as the only way and to not use
SCU based detection at all. Even if DT /cpu node based detection
fails, it continues with a single core
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

There are some redundant codes in the CPUINIT section that was caused by
some codes not be organized well in "headsmp.S". Currently all the codes
in "headsmp.S" were put into CPUINIT section. But actually it doesn't
need to be loacted in CPUINIT section. There is no fuction access them
in CPUINIT section and we will relocate them to IRAM.

These codes also caused some unnecessary functions that access these
codes been put into CPUINIT section too. This patch clean it up and put
them into normal text section.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The tegra_cpu_die was be executed by the CPU itslf. So the clock gating
procedure won't be executed after the CPU hardware shutdown code. Moving
the clock gating procedure to tegra_cpu_kill that will be run by another
CPU after the CPU died.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Updating the cache maintenance order before CPU shutdown when doing CPU
hotplug.
The old order:
* clean L1 by flush_cache_all
* exit SMP
* CPU shutdown
Adapt to:
* disable L1 data cache by clear C bit
* clean L1 by v7_flush_dcache_louis
* exit SMP
* CPU shutdown

For CPU hotplug case, it's no need to do "flush_cache_all". And we should
disable L1 data cache before clean L1 data cache. Then leaving the SMP
coherency.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The power up sequence is different on the cold boot CPU and the CPU
that resumed from the hotplug. For the cold boot CPU, it was been power
gated as default. To power up the cold boot CPU, the power should be
un-gated by un toggling the power gate register manually.

For the CPU that resumed from the hotplug, after un-halted the CPU. The
flow controller will un-gate the power of the CPU. No need to manually
control, just wait the power be resumed and continue the power up
sequence after the CPU power is ready.

Based on the work by:
Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

tegra_cpu_init/exit will be called every time one cpu core is online or
offline. And all cpu cores share same clocks, redundant clk_get/put
wast time,  so I move them out.
Signed-off-by: NRichard Zhao <linuxzsc@gmail.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Fix:

warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_754327 which has unmet direct dependencies (CPU_V7 && SMP)
warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_742230 which has unmet direct dependencies (CPU_V7 && SMP)

by selecting options only if SMP.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

No need to be public. Checked with:
  $ touch arch/arm/mach-tegra/*[ch] && make C=1
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Move arch/arm/mach-tegra/timer.c to drivers/clocksource/tegra20_timer.c
so that the code is co-located with other clocksource drivers, and to
reduce the size of the mach-tegra directory.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The clockevent core is able to figure out the best mult and shift,
calculate min_delta_ns and max_delta_ns, with the necessary info passed
into clockevents_config_and_register().  Use this combined configure
and register function where possible to make the codes less error prone
and gain some positive diff stat.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: NAnton Vorontsov <cbouatmailru@gmail.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Tested-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: David Brown <davidb@codeaurora.org>
Tested-by: NTony Lindgren <tony@atomide.com>
Acked-by: NBarry Song <baohua.song@csr.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NTony Prisk <linux@prisktech.co.nz>
Cc: Lennert Buytenhek <buytenh@wantstofly.org>
Cc: Wan ZongShun <mcuos.com@gmail.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Now that we have GIC moved to drivers/irqchip and all GIC DT init for
platforms using irqchip_init, move gic.h and update the remaining
includes.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>

Convert all GIC DT initialization over to use common irqchip_init
function.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>

Now that the GIC initialization sets up the handle_arch_irq pointer, we
can remove it for all machines and make it static.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NArnd Bergmann <arnd@arndb.de>

In preparation of moving gic code to drivers/irqchip, remove the direct
platform dependencies on gic_raise_softirq. Move the setup of
smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask
function to trigger wake-up IPIs.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
markings need to be removed.

This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.

Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.

Cc: Bill Pemberton <wfp5p@virginia.edu>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.

This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html

Includes mach-omap2 fixes from Igor Grinberg.
Tested-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NStephen Warren <swarren@nvidia.com>