Initial device tree for the Artpec-6 SoC.
Signed-off-by: NLars Persson <larper@axis.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This adds device tree bindings for the Artpec-6 SoC.
Signed-off-by: NLars Persson <larper@axis.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'v4.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Assorted bunch of 32bit Rockchip devicetree changes. More clocks,
nodes and fixes like the increased drive-strength on the firefly.
Most interesting is maybe the enablement of the pl330 option
for handling the broken flushp operation that is present on the
current Rockchip SoCs. Together with the driver-side enablement
this should give us working dma finally.

* tag 'v4.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (30 commits)
  ARM: dts: cros-ec-keyboard: Add LOCK key to keyboard matrix
  ARM: dts: rockchip: replace gpio-key,wakeup with wakeup-source property
  ARM: dts: rockchip: add arm,pl330-broken-no-flushp quirk for rk3036 SoCs
  ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3xxx platform
  ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3288 platform
  dt-bindings: rockchip-dw-mshc: add RK3036 dw-mshc description
  ARM: dts: rockchip: increase the mclk_fs to 512 for kylin board
  ARM: dts: rockchip: support the spi for rk3036
  ARM: dts: rockchip: add mclk for rt5616 on rk3036 kylin board
  ARM: dts: rockchip: add the leds control for rk3036-kylin board
  ARM: dts: rockchip: add tsadc node
  clk: rockchip: Add new id for rk3066 tsadc clock
  ARM: dts: rockchip: add clock-cells for usb phy nodes
  ARM: dts: rockchip: Assign RK3288 EDP_24M input centrally
  ARM: dts: rockchip: add soc-specific compatibles for rk3036 SoCs
  ARM: dts: rockchip: Bump sd card pin drive strength up on firefly boards
  dt-bindings: rockchip-dw-mshc: add RK3368 dw-mshc description
  ARM: dts: rockchip: Add the SDIO wifi on Radxa Rock2 square
  ARM: dts: rockchip: Add the iodomains for the Rock2 SOM
  ARM: dts: rockchip: add rk3288 mipi_dsi nodes
  ...
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'stm32-dt-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/dt

Highlights:
-----------
 - Add DMA controller node to stm32f429 MCU
 - Add pinctrl & gpio nodes to stm32f429 MCU
 - Remap stm32429-eval board SD-Ram to 0x0 for performance boost

* tag 'stm32-dt-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
  ARM: dts: stm32f429: Boost perfs by remapping SDRAM Bank 1 to 0x0
  ARM: dts: Add leds support to STM32F429 boards
  ARM: dts: Add USART1 pin config to STM32F429 boards
  ARM: dts: Add pinctrl node to STM32F429
  includes: dt-bindings: Add STM32F429 pinctrl DT bindings
  ARM: dts: Add STM32 DMA support for STM32F429 MCU
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt

Few updates for ARM VExpress/Juno platforms

1. GICv3 support on Foundation models

2. Support for Juno R2 board

3. Support for ARM HDLCD on all Juno platforms

* tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: Add HDLCD support on Juno platforms
  Documentation: drm: Add DT bindings for ARM HDLCD
  arm64: dts: Add support for Juno r2 board
  arm64: dts: move juno pcie-controller to base file
  arm64: dts: add .dts for GICv3 Foundation model
  arm64: dts: split Foundation model dts to put the GIC separately
  arm64: dts: Foundation model: increase GICC region to allow EOImode=1
  arm64: dts: prepare foundation-v8.dts to cope with GICv3
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge DT changes for lpc32xx from Vladimir Zapolskiy:

"The changes add description of clock providers and clock consumers,
define default irq types of SoC controllers and add PHY3250 board
regulators.

I'm adding an official LPC32xx maintainer Roland to Cc, however he seems
to be unresponsive for a quite long time (since 2014)."

* 'lpc32xx/dt' of https://github.com/vzapolskiy/linux:
  arm: dts: phy3250: add SD fixed regulator
  arm: dts: phy3250: add lcd and backlight fixed regulators
  arm: dts: lpc32xx: assign interrupt types
  arm: dts: lpc32xx: remove clock frequency property from UART device nodes
  arm: dts: lpc32xx: add USB clock controller
  arm: dts: lpc32xx: add clock properties to device nodes
  arm: dts: lpc32xx: add clock controller device node
  arm: dts: lpc32xx: add device nodes for external oscillators
  dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it
Signed-off-by: NOlof Johansson <olof@lixom.net>

Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy
"gpio-key,wakeup" boolean property to enable gpio buttons as wakeup
source.

Few dts files assign value "1" to gpio-key,wakeup which is incorrect.
Since the presence of the boolean property indicates it is enabled,
value of "0" or "1" have no significance.

This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property which inturn fixes the above mentioned issue.
Reviewed-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

mvebu dt for 4.6 (part 1)

- Improve Armada 38x device tree (SATA and XHCI)
- Fix SD Card and audio support for OpenRD board
- Provide template for RS-232/485 configuration for the same board
- Use a common dtsi file for linkstation boards
- Add support for Buffalo Linkstation LS-QVL

* tag 'mvebu-dt-4.6-1' of git://git.infradead.org/linux-mvebu:
  ARM: dts: kirkwood: add device tree for buffalo linkstation ls-qvl
  ARM: dts: kirkwood: fix audio for OpenRD clients
  ARM: dts: kirkwood: provide template for RS-232/485 configuration for OpenRD
  ARM: dts: kirkwood: split lswvl dts to linkstation lsvl and lswvl
  ARM: dts: kirkwood: split lswxl dts to linkstation lswsxl and lswxl
  ARM: dts: kirkwood: relicense dts of ls-wvl/vl and ls-wxl/wsxl under GPLv2/X11
  ARM: dts: kirkwood: fix SD slot default configuration for OpenRD
  ARM: dts: kirkwood: fix pin names for UART/SD selection for OpenRD
  ARM: dts: armada-370: Update the mpp63 function in the device tree on Armada 370
  ARM: dts: armada-38x: use usb-nop-xceiv PHY for the xhci nodes on Armada 388 GP
  ARM: dts: armada-38x: use regulator-boot-on for SATA regulators on Armada 388 GP
  ARM: dts: armada-38x: adjust board name and compatible for Armada 388 GP
Signed-off-by: NOlof Johansson <olof@lixom.net>

STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc0000000 to 0x0,
by writing 0x4 to SYSCFG_MEMRMP register.

As mentionned in the reference manual (see chapter 9.3.1), the performance
gain is really interresting:
"In remap mode at address 0x0000 0000, the CPU can access the external
memory via ICode bus instead of System bus which boosts up the
performance."

These are the dhrystone results with and without the remap enabled:
Default (SDRAM in 0xc0000000):
---------------------------------
Microseconds for one run through Dhrystone:   31.8
Dhrystones per Second:                      31416.9

Remap (SDRAM in 0x0000000):
-----------------------------
Microseconds for one run through Dhrystone:   20.6
Dhrystones per Second:                      48520.1

This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL
board, and also set the dma-range property as the other masters than the M4
CPU still see SDRAM in 0xc0000000.

Note that the Discovery board cannot benefit from this feature, since the
SDRAM is connected to Bank 2.
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

The change adds fixed voltage regulator for SD controller, ARM MMCI
controller driver uses it to control card power management.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

Phytec PHY3250 board has GPIO controlled regulators for LCD and
backlight, add their descriptions to board DTS file.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

LPC32xx interrupt controller has two cells, instead of zero
specify proper irq types for all consumers.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

If clock-frequency property is given, then it substitutes calculation
of supplying clock frequency from parent clock, this may break UART,
if parent clock is given and managed by common clock framework.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

The change adds device node of LPC32xx USB clock controller and adds
clock properties to USB OHCI, USB device and I2C controller to USB phy
device nodes.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

The change adds clock properties to all described peripheral devices,
clock ids are taken from dt-bindings/clock/lpc32xx-clock.h

Some existing drivers expect to get clock names, in those cases
clock-names are added as well.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part
of system control block (SCB). CPC is supplied by two external
oscillators and it manages core and most of peripheral clocks, the
change adds SCB and CPC descriptions to shared LPC32xx dtsi file.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

NXP LPC32xx SoC has two external oscillators - one is mandatory and
always on 32768 Hz oscillator and one optional 10-20MHz oscillator,
which is practically always present on LPC32xx boards, because its
presence is needed to supply USB controller clock and by default it
supplies ARM and most of the peripheral clocks, LPC32xx User's Manual
references it as a main oscillator.

The change adds device nodes for both oscillators, frequency of
the main oscillator is selected to be 13MHz by default, this variant
is found on all LPC32xx reference boards.

The device nodes for external oscillators are needed to describe input
clocks of LPC32xx clock controller.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

Create a separate folder for device tree bindings of NXP SoCs devices,
and move lpc32xx.txt to it.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

The LOCK key is at KSO9/KSI3 for Chromebook Flip and other devices
that use the Chrome OS EC keyboard matrix.
Signed-off-by: NJames Chao <james_chao@asus.com>
Signed-off-by: NYH Huang <yh.huang@mediatek.com>
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

ARM's Juno platforms have two HDLCD controllers, each linked to an NXP
TDA19988 HDMI transmitter that provides output encoding. Add them
to the device tree.
Acked-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy
"gpio-key,wakeup" boolean property to enable gpio buttons as wakeup
source.

Few dts files assign value "1" to gpio-key,wakeup and in one instance a
value "0" is assigned probably assuming it won't be enabled as a wakeup
source. Since the presence of the boolean property indicates it is
enabled, value of "0" have no value.

This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property which inturn fixes the above mentioned issue.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by
Cortex A72 cores.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

The PCIe controller is found on all Juno SoC version. However it's not
functional on R0 due to some hardware bug.

In preparation to add Juno R2 support, this patch moves the
pcie-controller defination to base DTS file. It's marked as disabled by
default and is enabled for Juno R1 explicitly.
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

The ARMv8 Foundation model sports a command line parameter to use
a GICv3 emulation instead of the default GICv2 interrupt controller.
Add a new .dts file which reuses most of the definitions of the
existing model while just adding the required properties for the
GICv3 node.

This allows the public Foundation model to run with a GICv3.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

The ARMv8 Foundation model can be run with a GICv2 or a GICv3.
To prepare for the GICv3 version of the .dts without code duplication,
move most of the nodes of the existing DT (except the GIC) into an
include file and just keep that include statement and the GIC node in
the current foundation-v8.dts.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

The Foundation model GIC mapping is wrong, as the GICC region should
be 8kB instead of 4kB (the model implements the GICv2 architecture).
This defect prevents the driver from switching to EOImode==1.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

To prepare the ARM foundation model to support GICv3, we adjust
the #address-cells property of the current GICv2 node to be
compatible with the two cells required for GICv3 later.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Add dts file to support Buffalo Linkstation LS-QVL,
which is marvell kirkwood based 4-bay 3.5" HDD NAS.
Product info:
  - (JPN) http://buffalo.jp/product/hdd/network/ls-qvl_r5/
  - (ENG) http://www.buffalotech.com/products/network-storage/home-and-small-office/linkstation-pro-quadSigned-off-by: NMario Lange <mario_lange@gmx.net>
Signed-off-by: NRoger Shimizu <rogershimizu@gmail.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Fix audio on kirkwood-openrd-client:

1) The audio-controller was left disabled.

2) The probe fails because cs42l51 is missing #sound-dai-cells.

	/sound/simple-audio-card,codec: could not get #sound-dai-cells for /ocp@f1000000/i2c@11000/cs42l51@4a
	asoc-simple-card sound: parse error -22
	asoc-simple-card: probe of sound failed with error -22

3) The mapping is incorrect:

	asoc-simple-card sound: cs42l51-hifi <-> spdif mapping ok

   should be:

	asoc-simple-card sound: cs42l51-hifi <-> i2s mapping ok
Reported-by: NRick Thomas <rbthomas@pobox.com>
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NRick Thomas <rbthomas@pobox.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Some OpenRD boards have RS-232 and RS-486 connectors wired, but using them
needs a custom DTB as the current DTB configures SD card slot instead.

This patch adds documentation into the DTS on how to change
the configuration.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

LS-WVL/VL are both kirkwood-6282 based NAS devices, which share
many MPP pins. However they are slightly different:
  - LS-WVL is 2-Bay NAS, and LS-VL is only 1-Bay.
  - There're two red LED indicator on LS-WVL to show when HDD fails,
    which is similar to LS-WXL, but there's no such on LS-VL.

So after the split, common part goes into .dtsi file:
  - kirkwood-linkstation-6282.dtsi
while all rest part goes into device specific .dts file:
  - kirkwood-linkstation-lsvl.dts
  - kirkwood-linkstation-lswvl.dts
Signed-off-by: NRoger Shimizu <rogershimizu@gmail.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

LS-WXL/WSXL are both kirkwood-6281 based 2-Bay NAS devices, which share
many MPP pins. However they are slightly different:
  - There're two red LED indicator on LS-WXL to show when HDD fails,
    but there's no such on LS-WSXL.
  - There's 4-level speed adjustable FAN on LS-WXL, but not LS-WSXL.

So after the split, common part goes into .dtsi file:
  - kirkwood-linkstation.dtsi
  - kirkwood-linkstation-duo-6281.dtsi
while all rest part goes into device specific .dts file:
  - kirkwood-linkstation-lswsxl.dts
  - kirkwood-linkstation-lswxl.dts
Signed-off-by: NRoger Shimizu <rogershimizu@gmail.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Signed-off-by: NRoger Shimizu <rogershimizu@gmail.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The SD card slot was enabled by default with legacy booting.
It does not work anymore with DT boot. Fix by providing GPIO configuration
that matches the old default.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The UART/SD pin names are swapped, fix that.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>