* pci/enumeration:
  PCI: Include PCI-to-PCIe bridges as "Downstream Ports"
  PCI: Improve __pci_read_base() robustness
  PCI: Short-circuit pci_device_is_present() for disconnected devices
  PCI/MSI: Skip disabling disconnected devices
  PCI: Don't attempt config access to disconnected devices
  PCI: Add device disconnected state
  PCI: Export PCI device config accessors

* pci/switchtec:
  switchtec: Add IOCTLs to the Switchtec driver
  switchtec: Add sysfs attributes to the Switchtec driver
  switchtec: Add user interface documentation
  MicroSemi Switchtec management interface driver

Conflicts:
	drivers/pci/Kconfig

* pci/host-thunder:
  PCI/ACPI: Add ThunderX pass2.x 2nd node MCFG quirk
  PCI/ACPI: Tidy up MCFG quirk whitespace
  PCI: Avoid generating invalid ThunderX2 DMA aliases
  PCI: Add device flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
  PCI: Apply Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices

* pci/host-rockchip:
  PCI: rockchip: Modularize
  PCI: Export pci_remap_iospace() and pci_unmap_iospace()
  PCI: rockchip: Add remove() support
  PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port
  PCI: rockchip: Advertise 128-byte Read Completion Boundary support
  PCI: rockchip: Make 'return 0' more obvious in probe()
  PCI: rockchip: Unindent rockchip_pcie_set_power_limit()
  PCI: rockchip: Handle regulator_get_current_limit() failure correctly

* pci/host-mvebu:
  PCI: mvebu: Avoid changing the SCC bit in the Link Status register

* pci/host-iproc:
  PCI: iproc: Add PCI_DOMAIN dependency to PCI Kconfig

* pci/host-imx6:
  PCI: imx6: Fix spelling mistake: "contol" -> "control"
  PCI: imx6: Do not switch speed if Gen2 is disabled
  PCI: imx6: Do not wait for speed change on i.MX7
  PCI: imx6: Allow probe deferral by reset GPIO
  PCI: imx6: Add code to support i.MX7D

* pci/host-hv:
  PCI: hv: Convert hv_pci_dev.refs from atomic_t to refcount_t
  PCI: hv: Allocate interrupt descriptors with GFP_ATOMIC
  PCI: hv: Specify CPU_AFFINITY_ALL for MSI affinity when >= 32 CPUs
  PCI: hv: Lock PCI bus on device eject
  PCI: hv: Properly handle PCI bus remove

* pci/host-faraday:
  PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver
  PCI: Add DT bindings for Faraday Technology PCI Host Bridge

* pci/host-designware:
  ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP
  MAINTAINERS: Add PCI Endpoint maintainer
  Documentation: PCI: Add userguide for PCI endpoint test function
  tools: PCI: Add sample test script to invoke pcitest
  tools: PCI: Add a userspace tool to test PCI endpoint
  Documentation: misc-devices: Add Documentation for pci-endpoint-test driver
  misc: Add host side PCI driver for PCI test function device
  PCI: Add device IDs for DRA74x and DRA72x
  dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access
  PCI: dwc: dra7xx: Workaround for errata id i870
  dt-bindings: PCI: dra7xx: Add DT bindings for PCI dra7xx EP mode
  PCI: dwc: dra7xx: Add EP mode support
  PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled independently
  dt-bindings: PCI: Add DT bindings for PCI designware EP mode
  PCI: dwc: designware: Add EP mode support
  Documentation: PCI: Add binding documentation for pci-test endpoint function
  PCI: endpoint: functions: Add an EP function to test PCI
  Documentation: PCI: Add specification for the *PCI test* function device
  PCI: endpoint: Create configfs entry for EPC device and EPF driver
  Documentation: PCI: Guide to use PCI endpoint configfs
  PCI: endpoint: Introduce configfs entry for configuring EP functions
  Documentation: PCI: Guide to use PCI Endpoint Core Layer
  PCI: endpoint: Add EP core layer to enable EP controller and EP functions
  PCI: dwc: dra7xx: Push request_irq() call to the bottom of probe
  PCI: dwc: designware: Move _unroll configurations to a separate function
  PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
  PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
  PCI: dwc: artpec6: Populate cpu_addr_fixup ops
  PCI: dwc: dra7xx: Populate cpu_addr_fixup ops
  PCI: dwc: designware: Add new *ops* for CPU addr fixup
  PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()
  PCI: dwc: Unindent dw_handle_msi_irq() loop
  PCI: dwc: Fix dw_pcie_ops NULL pointer dereference
  PCI: dwc: Select PCI_HOST_COMMON for hisi
  PCI: thunder-pem: Fix legacy firmware PEM-specific resources
  PCI: thunder-pem: Add legacy firmware support for Cavium ThunderX host controller
  PCI: thunder-pem: Use Cavium assigned hardware ID for ThunderX host controller
  PCI: iproc: Save host bridge window resource in struct iproc_pcie
  PCI/ASPM: Always set link->downstream to avoid NULL dereference on remove
  PCI: Prevent VPD access for QLogic ISP2722
  PCI: exynos: Initialize elbi_base even when using PHY framework

The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should be
set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO in RC
mode. However in EP mode, the host system is not able to access the
MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add maintainer for the newly introduced PCI Endpoint framework.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add documentation to help users use pci-epf-test function driver and
pci_endpoint_test host driver for testing PCI.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add a simple test script that invokes the pcitest userspace tool to perform
all the PCI endpoint tests (BAR tests, interrupt tests, read tests, write
tests and copy tests).
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add a userspace tool to invoke the ioctls exposed by the PCI endpoint test
driver to perform various PCI tests.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add Documentation for pci-endpoint-test driver.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add PCI endpoint test driver that can verify base address register, legacy
interrupt/MSI interrupt and read/write/copy buffers between host and
device. The corresponding pci-epf-test function driver should be used on
the EP side.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add device IDs for DRA74x and DRA72x devices. These devices have
configurable PCI endpoint.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Update device tree binding documentation of TI's dra7xx PCI controller to
include property for enabling unaligned mem access.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

According to errata i870, access to the PCIe slave port that are not 32-bit
aligned will result in incorrect mapping to TLP Address and Byte enable
fields.

Accessing non 32-bit aligned data causes incorrect data in the target
buffer if memcpy is used. Implement the workaround for this errata here.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add device tree binding documentation for PCI dra7xx EP mode.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The PCIe controller integrated in dra7xx SoCs is capable of operating in
endpoint mode. Add endpoint mode support to dra7xx driver.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

No functional change. Split dra7xx_pcie_enable_interrupts() into
dra7xx_pcie_enable_wrapper_interrupts() and
dra7xx_pcie_enable_msi_interrupts() so that wrapper interrupts and MSI
interrupts can be enabled independently.  This is in preparation for adding
EP mode support to dra7xx driver since EP mode doesn't have to enable
msi_interrupts.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add device tree binding documentation for PCI designware EP mode.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRob Herring <robh@kernel.org>

Add endpoint mode support to designware driver. This uses the EP Core layer
introduced recently to add endpoint mode support.  *Any* function driver
can now use this designware device in order to achieve the EP
functionality.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Trivial fix to spelling mistake in dev_err message
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRichard Zhu <hongxing.Zhu@nxp.com>

Currently SoCs pass2.x do not emulate EA headers for ACPI boot method at
all.  However, for pass2.x some devices (like EDAC) advertise incorrect
base addresses in their BARs which results in driver probe failure during
resource request.  Since all problematic blocks are on 2nd NUMA node under
domain 10 add necessary quirk entry to obtain BAR addresses correction
using EA header emulation.

Fixes: 44f22bd9 ("PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller")
Signed-off-by: NTomasz Nowicki <tn@semihalf.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRobert Richter <rrichter@cavium.com>
CC: stable@vger.kernel.org	# v4.10+

With no blank lines, it's not obvious where the macro definitions end and
the uses begin.  Add some blank lines and reorder the ThunderX definitions.
No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v4.10+

Now that we've exported pci_remap_iospace() and added proper remove()
support, there's no reason this can't be a loadable module.
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Lin <shawn.lin@rock-chips.com>

These are useful for PCIe host drivers, and those drivers can be modules.

[bhelgaas: don't remove __weak; it's removed elsewhere]
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Lin <shawn.lin@rock-chips.com>

Currently, if we try to unbind the platform device, the remove will
succeed, but the removal won't undo most of the registration, leaving
partially-configured PCI devices in the system.

This allows, for example, a simple 'lspci' to crash the system, as it will
try to touch the freed (via devm_*) driver structures, e.g., on RK3399:

  # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind
  # lspci

So let's implement device remove().
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NShawn Lin <shawn.lin@rock-chips.com>

A PCI/PCI-X to PCI Express bridge, sometimes referred to as a "reverse
bridge", is a bridge with conventional PCI or PCI-X on its primary side and
a PCI Express Port on its secondary (downstream) side.

That PCIe Port is a Downstream Port and could be connected to a slot, just
like a Root Port or a Switch Downstream Port.  Make pcie_downstream_port()
return true for them, so we can access the Slot registers in the PCIe
capability.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Local variables 'l' and 'sz' are uninitialized.  Normally, they would
be initialized by pci_read_config_dword() but when an error occurs,
some drivers immediately return an error code, which leaves the
argument uninitialized.

Provide a safe initial value to make the code more robust.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

refcount_t type and corresponding API should be used instead of atomic_t
when the variable is used as a reference counter.  This allows to avoid
accidental refcounter overflows that might lead to use-after-free
situations.
Signed-off-by: NElena Reshetova <elena.reshetova@intel.com>
Signed-off-by: NHans Liljestrand <ishkamiel@gmail.com>
Signed-off-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NDavid Windsor <dwindsor@gmail.com>
Reviewed-by: NStephen Hemminger <sthemmin@microsoft.com>

On Cavium ThunderX2 arm64 SoCs (formerly known as Broadcom Vulcan), the PCI
topology is slightly unusual.  For a multi-node system, it looks like:

    00:00.0 PCI bridge to [bus 01-1e]
    01:0a.0 PCI-to-PCIe bridge to [bus 02-04]
    02:00.0 PCIe Root Port bridge to [bus 03-04] (XLATE_ROOT)
    03:00.0 PCIe Endpoint

pci_for_each_dma_alias() assumes IOMMU translation is done at the root of
the PCI hierarchy.  It generates 03:00.0, 01:0a.0, and 00:00.0 as DMA
aliases for 03:00.0 because buses 01 and 00 are non-PCIe buses that don't
carry the Requester ID.

Because the ThunderX2 IOMMU is at 02:00.0, the Requester IDs 01:0a.0 and
00:00.0 are never valid for the endpoint.  This quirk stops alias
generation at the XLATE_ROOT bridge so we won't generate 01:0a.0 or
00:00.0.

The current IOMMU code only maps the last alias (this is a separate bug in
itself).  Prior to this quirk, we only created IOMMU mappings for the
invalid Requester ID 00:00:0, which never matched any DMA transactions.

With this quirk, we create IOMMU mappings for a valid Requester ID, which
fixes devices with no aliases but leaves devices with aliases still broken.

The last alias for the endpoint is also used by the ARM GICv3 MSI-X code.
Without this quirk, the GIC Interrupt Translation Tables are setup with the
invalid Requester ID, and the MSI-X generated by the device fails to be
translated and routed.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=195447Signed-off-by: NJayachandran C <jnair@caviumnetworks.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NRobin Murphy <robin.murphy@arm.com>
Acked-by: NDavid Daney <david.daney@cavium.com>

Add a new quirk flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT to limit the DMA alias
search to go no further than the bridge where the IOMMU unit is attached.

The flag will be used to indicate a bridge device which forwards the
address translation requests to the IOMMU, i.e., where the interrupt and
DMA requests leave the PCIe hierarchy and go into the system blocks.

Usually this happens at the PCI RC, so this flag is not needed.  But on
systems where there are bridges that introduce aliases above the IOMMU,
this flag prevents pci_for_each_dma_alias() from generating aliases that
the IOMMU will never see.

The function pci_for_each_dma_alias() is updated to stop when it see a
bridge with this flag set.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=195447Signed-off-by: NJayachandran C <jnair@caviumnetworks.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NRobin Murphy <robin.murphy@arm.com>
Acked-by: NDavid Daney <david.daney@cavium.com>

Add a couple of special IOCTLs to:

* Inform userspace of firmware partition locations
* Pass event counts and allow userspace to wait on events
* Translate PFF numbers used by the switch to port numbers

[Dan Carpenter <dan.carpenter@oracle.com>: fix off-by-one in
ioctl_event_ctl()]
Tested-by: NKrishna Dhulipala <krishnad@fb.com>
Signed-off-by: NLogan Gunthorpe <logang@deltatee.com>
Signed-off-by: NStephen Bates <stephen.bates@microsemi.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NWei Zhang <wzhang@fb.com>
Reviewed-by: NJens Axboe <axboe@fb.com>

Add a few read-only sysfs attributes which provide some device information
that is exposed from the devices, primarily component and device names and
versions.

These are documented in Documentation/ABI/testing/sysfs-class-switchtec.
Tested-by: NKrishna Dhulipala <krishnad@fb.com>
Signed-off-by: NLogan Gunthorpe <logang@deltatee.com>
Signed-off-by: NStephen Bates <stephen.bates@microsemi.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NWei Zhang <wzhang@fb.com>
Reviewed-by: NJens Axboe <axboe@fb.com>
Reviewed-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add standard documentation for the sysfs switchtec attributes and a RST
formatted text file which documents the char device interface.  Jonathan
Corbet has indicated he will move this to a new user-space developer
documentation book once it's created.
Tested-by: NKrishna Dhulipala <krishnad@fb.com>
Signed-off-by: NLogan Gunthorpe <logang@deltatee.com>
Signed-off-by: NStephen Bates <stephen.bates@microsemi.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NWei Zhang <wzhang@fb.com>
Reviewed-by: NJens Axboe <axboe@fb.com>