It's pretty similar to the STM32F429, but there are some
subtle changes required to boot successfully.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc0000000 to 0x0,
by writing 0x4 to SYSCFG_MEMRMP register.

As mentionned in the reference manual (see chapter 9.3.1), the performance
gain is really interresting:
"In remap mode at address 0x0000 0000, the CPU can access the external
memory via ICode bus instead of System bus which boosts up the
performance."

These are the dhrystone results with and without the remap enabled:
Default (SDRAM in 0xc0000000):
---------------------------------
Microseconds for one run through Dhrystone:   31.8
Dhrystones per Second:                      31416.9

Remap (SDRAM in 0x0000000):
-----------------------------
Microseconds for one run through Dhrystone:   20.6
Dhrystones per Second:                      48520.1

This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL
board, and also set the dma-range property as the other masters than the M4
CPU still see SDRAM in 0xc0000000.

Note that the Discovery board cannot benefit from this feature, since the
SDRAM is connected to Bank 2.
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

This patch adds STM32 DMA bindings for STM32F429.
Signed-off-by: NM'boumba Cedric Madianga <cedric.madianga@gmail.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

On r8a7740/armadillo, actual clock rates are ca. 4% lower than reported
by /sys/kernel/debug/clk/clk_summary. Correct the extal1 frequency from
25 MHz to 24 MHz to fix this.

This matches the Armadillo-800 EVA Product Manual, which claims the main
crystal runs at 24 MHz, and the old legacy/reference board code.

Fixes: 25aa7ba3 ("ARM: shmobile: armadillo800eva: Sync DTS")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Enable PCIe DT node and fill PCIe DT node with regulator, pinctrl and reset
GPIO, to use the PCIe on the ifc6410 board.
Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add the PCIe DT node so that it can probe and be used.
Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The device tree version of Versatile AP/PB never had LED support
so we are missing LEDs from our hardware boards. Add this as
syscon LEDs like we did for Integrator and Juno. We need to
spawn devices in the syscon with "simple-mfd" for this to work.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

According to datasheet, the registers space of SDHC controller is 1Kb,
not '0x1000', the correct value should be '0x400'. Bracket interrupt
numbers individually per recommendations.
Signed-off-by: NRoman Volkov <rvolkov@v1ros.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Since WM8650 has the same 'WMT' SDHC controller as WM8505, and the driver
is already in the kernel, this node enables the controller support for
WM8650
Signed-off-by: NRoman Volkov <rvolkov@v1ros.org>
Reviewed-by: NAlexey Charkov <alchark@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Commit 0976c946
"arm/versatile: Fix versatile irq specifications"
has an off-by-one error on the Versatile AB that has
been regressing the Versatile AB hardware for some time.

However it seems like the interrupt assignments have
never been correct and I have now adjusted them according
to the specification. The masks for the valid interrupts
made it impossible to assign the right SIC interrupt
for the MMCI, so I went in and fixed these to correspond
to the specifications, and added references if anyone
wants to double-check.

Due to the Versatile PB including the Versatile AB
as a base DTS file, we need to override and correct
some values to correspond to the actual changes in the
hardware.

For the Versatile PB I don't think the IRQ line
assignment for MMCI has ever been correct for either of
the two MMCI blocks. It would be nice if someone with the
physical PB board could test this.

Patch tested on the Versatile AB, QEMU for Versatile AB
and QEMU for Versatile PB.

Cc: Rob Herring <robh@kernel.org>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: stable@vger.kernel.org
Fixes: 0976c946 ("arm/versatile: Fix versatile irq specifications")
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The Nomadik has sporadic crashes because of these latencies, setting
them to max makes the platform work nicely, so use this values for
now.

These latencies were set to 2 since the Nomadik platform was merged,
but I suspect they never took effect until the right size and
associativity for the cache was specified in the device tree and
that is why the crash comes now.

Cc: stable@vger.kernel.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The pinctrl group ipu2grp is a leftover from the previous iomuxc DT
cleanup.  It's not used by anyone now.  More importantly, it's getting
in the way of saving the unnecessary pinfunc container node from the
board dts files that include imx6q.dtsi.

Let's clean it up.
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
Tested-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

As of commit e488ca9f ("doc: dt: mtd: partitions: add compatible
property to "partitions" node"), the "partitions" subnode of an SPI
FLASH device node must have a compatible property. The partitions are no
longer detected if it is not present.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

As of commit e488ca9f ("doc: dt: mtd: partitions: add compatible
property to "partitions" node"), the "partitions" subnode of an SPI
FLASH device node must have a compatible property. The partitions are no
longer detected if it is not present.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

As of commit e488ca9f ("doc: dt: mtd: partitions: add compatible
property to "partitions" node"), the "partitions" subnode of an SPI
FLASH device node must have a compatible property. The partitions are no
longer detected if it is not present.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

As of commit e488ca9f ("doc: dt: mtd: partitions: add compatible
property to "partitions" node"), the "partitions" subnode of an SPI
FLASH device node must have a compatible property. The partitions are no
longer detected if it is not present.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

As of commit e488ca9f ("doc: dt: mtd: partitions: add compatible
property to "partitions" node"), the "partitions" subnode of an SPI
FLASH device node must have a compatible property. The partitions are no
longer detected if it is not present.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

As of commit e488ca9f ("doc: dt: mtd: partitions: add compatible
property to "partitions" node"), the "partitions" subnode of an SPI
FLASH device node must have a compatible property. The partitions are no
longer detected if it is not present.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

With this patch we add the watchdog node in the meson8b DTS file.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

Add the blue status LED to the Hardkernel Odroid C1 board DTS.

Signed-off-by: <edward.cragg@codethink.co.uk>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

These will be used for enabling UART1, SPI1, and SPI2.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The Pi 2 B ends up like a Pi 1 B+, with the same peripherals and
pinout, but the CPU and memory layout changed to use the 2836.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

For Raspberry Pi 2, we want to use the same general pin assignment
bits, but need to use bcm2836.dtsi for the CPU instead.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The set of peripherals remained constant across bcm2835 (Raspberry Pi
1) and bcm2836 (Raspberry Pi 2), but the CPU was swapped out.  Split
the files so that we can include just peripheral setup in 2836.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The L2 cache comes up in a "safe mode" on the PB11MPCore, as
it has several issues. This sets it up properly with the right
size and associativity, also requiring the outer sync to be
disabled for the machine to boot properly.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

G2D device is always available and doesn't depend on any external (board
specific) peripherals, so it can be unconditionally enabled.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

G2D device and it's SYSMMU belongs to LCD0 power domain on Exynos 4210,
so add missing power-domains property to G2D device node (G2D's SYSMMU is
already bound to LCD0 power domain).
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

On Exynos 4210 MDMA1 device belongs to LCD0 power domain, so add proper
power-domains property. On Exynos 4x12, it belongs to TOP power domain,
which is always enabled, thus require no assignment in exynos4x12.dtsi.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

The <dt-bindings/gpio/gpio.h> header is already included in the
exynos4412-odroid-common DTSI so there's no need to do it again
in the DTS file.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

PDMA for UART devices seems not to be working properly on Exynos 4210
revision 0 used in Universal C210 boards, so disable it to let one to
use UART devices (driver defaults to PIO mode if DMA is not present).
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

DWC3 device found on Exynos SoCs cannot work in OTG mode alone, because
it lacks some OTG related control part. OTG mode operation is possible
only with external hardware logic (usually GPIO-based) specific to
the board. Right now, however, there is no driver for such logic and no
bindings, so the OTG mode is dysfunctional at all (this means that it
doesn't work as a peripheral nor as a host). This patch sets the operation
mode to peripheral to get DWC3_1 device at least somehow working. This can
be later updated, when proper OTG driver and bindings get developed.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

This patch adds device node for Rotator device and it's SYSMMU to Exynos
542x device tree file.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

This patch adds device node for Rotator device to Exynos 5250 device
tree file.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Rotator device and it's SYSMMU belongs to different power domains
on various Exynos4 SoC revisions: LCD0 for 4210 and TOP for 4x12. This
patch fixes this by moving power-domains property to exynos4210.dtsi. TOP
power domain is always enabled and it is not represented in DTS.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

This patch adds device node for Rotator device to Exynos 4210 and 4x12
device tree files.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Enable Pseudo Random Number Generator (PRNG) on Trats2 board. This
allows using hardware random number generator:
$ echo exynos > /sys/class/misc/hw_random/rng_current
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>