1. 30 9月, 2013 1 次提交
    • W
      ARM: atomics: prefetch the destination word for write prior to strex · f38d999c
      Will Deacon 提交于
      The cost of changing a cacheline from shared to exclusive state can be
      significant, especially when this is triggered by an exclusive store,
      since it may result in having to retry the transaction.
      
      This patch prefixes our atomic access implementations with pldw
      instructions (on CPUs which support them) to try and grab the line in
      exclusive state from the start. Only the barrier-less functions are
      updated, since memory barriers can limit the usefulness of prefetching
      data.
      Acked-by: NNicolas Pitre <nico@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      f38d999c
  2. 04 4月, 2013 1 次提交
  3. 05 7月, 2012 1 次提交
  4. 29 3月, 2012 1 次提交
  5. 27 7月, 2011 3 次提交
  6. 09 7月, 2010 2 次提交
    • W
      ARM: 6212/1: atomic ops: add memory constraints to inline asm · 398aa668
      Will Deacon 提交于
      Currently, the 32-bit and 64-bit atomic operations on ARM do not
      include memory constraints in the inline assembly blocks. In the
      case of barrier-less operations [for example, atomic_add], this
      means that the compiler may constant fold values which have actually
      been modified by a call to an atomic operation.
      
      This issue can be observed in the atomic64_test routine in
      <kernel root>/lib/atomic64_test.c:
      
      00000000 <test_atomic64>:
         0:	e1a0c00d 	mov	ip, sp
         4:	e92dd830 	push	{r4, r5, fp, ip, lr, pc}
         8:	e24cb004 	sub	fp, ip, #4
         c:	e24dd008 	sub	sp, sp, #8
        10:	e24b3014 	sub	r3, fp, #20
        14:	e30d000d 	movw	r0, #53261	; 0xd00d
        18:	e3011337 	movw	r1, #4919	; 0x1337
        1c:	e34c0001 	movt	r0, #49153	; 0xc001
        20:	e34a1aa3 	movt	r1, #43683	; 0xaaa3
        24:	e16300f8 	strd	r0, [r3, #-8]!
        28:	e30c0afe 	movw	r0, #51966	; 0xcafe
        2c:	e30b1eef 	movw	r1, #48879	; 0xbeef
        30:	e34d0eaf 	movt	r0, #57007	; 0xdeaf
        34:	e34d1ead 	movt	r1, #57005	; 0xdead
        38:	e1b34f9f 	ldrexd	r4, [r3]
        3c:	e1a34f90 	strexd	r4, r0, [r3]
        40:	e3340000 	teq	r4, #0
        44:	1afffffb 	bne	38 <test_atomic64+0x38>
        48:	e59f0004 	ldr	r0, [pc, #4]	; 54 <test_atomic64+0x54>
        4c:	e3a0101e 	mov	r1, #30
        50:	ebfffffe 	bl	0 <__bug>
        54:	00000000 	.word	0x00000000
      
      The atomic64_set (0x38-0x44) writes to the atomic64_t, but the
      compiler doesn't see this, assumes the test condition is always
      false and generates an unconditional branch to __bug. The rest of the
      test is optimised away.
      
      This patch adds suitable memory constraints to the atomic operations on ARM
      to ensure that the compiler is informed of the correct data hazards. We have
      to use the "Qo" constraints to avoid hitting the GCC anomaly described at
      http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44492 , where the compiler
      makes assumptions about the writeback in the addressing mode used by the
      inline assembly. These constraints forbid the use of auto{inc,dec} addressing
      modes, so it doesn't matter if we don't use the operand exactly once.
      
      Cc: stable@kernel.org
      Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      398aa668
    • W
      ARM: 6211/1: atomic ops: fix register constraints for atomic64_add_unless · 068de8d1
      Will Deacon 提交于
      The atomic64_add_unless function compares an atomic variable with
      a given value and, if they are not equal, adds another given value
      to the atomic variable. The function returns zero if the addition
      did not occur and non-zero otherwise.
      
      On ARM, the return value is initialised to 1 in C code. Inline assembly
      code then performs the atomic64_add_unless operation, setting the
      return value to 0 iff the addition does not occur. This means that
      when the addition *does* occur, the value of ret must be preserved
      across the inline assembly and therefore requires a "+r" constraint
      rather than the current one of "=&r".
      
      Thanks to Nicolas Pitre for helping to spot this.
      
      Cc: stable@kernel.org
      Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      068de8d1
  7. 17 5月, 2010 1 次提交
  8. 16 2月, 2010 1 次提交
  9. 19 9月, 2009 1 次提交
    • C
      Clear the exclusive monitor when returning from an exception · 200b812d
      Catalin Marinas 提交于
      The patch adds a CLREX or dummy STREX to the exception return path. This
      is needed because several atomic/locking operations use a pair of
      LDREX/STREXEQ and the EQ condition may not always be satisfied. This
      would leave the exclusive monitor status set and may cause problems with
      atomic/locking operations in the interrupted code.
      
      With this patch, the atomic_set() operation can be a simple STR
      instruction (on SMP systems, the global exclusive monitor is cleared by
      STR anyway). Clearing the exclusive monitor during context switch is no
      longer needed as this is handled by the exception return path anyway.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Reported-by: NJamie Lokier <jamie@shareable.org>
      200b812d
  10. 26 7月, 2009 1 次提交
  11. 12 6月, 2009 1 次提交
  12. 29 5月, 2009 1 次提交
  13. 07 1月, 2009 1 次提交
  14. 03 8月, 2008 1 次提交
  15. 09 5月, 2007 1 次提交
  16. 16 3月, 2007 1 次提交
    • S
      [ARM] 4264/1: ldrex/strex syntax errors with recent compilers · 0803c30c
      Stelian Pop 提交于
      Trying to build some code using atomic_clear_mask() on a ARM v6
      processor with a recent compiler (tried with gcc version 4.1.1
      (CodeSourcery ARM Sourcery G++ 2006q3-26), but
      all gcc > 4.1 might be affected) results in the following:
      
      /tmp/ccWKLJV8.s: Assembler messages:
      /tmp/ccWKLJV8.s:581: Error: instruction does not accept this addressing
      mode -- `ldrex r0,r3'
      /tmp/ccWKLJV8.s:583: Error: instruction does not accept this addressing
      mode -- `strex r1,r0,r3'
      
      Older gcc (like gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) have no problem
      with this.
      
      The patch below fixes the compile error. I also verified that gcc-4.0.0 generates identical code using both forms.
      Signed-off-by: NStelian Pop <stelian@popies.net>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      0803c30c
  17. 25 9月, 2006 1 次提交
  18. 26 4月, 2006 1 次提交
  19. 10 1月, 2006 1 次提交
  20. 07 1月, 2006 1 次提交
  21. 17 11月, 2005 2 次提交
  22. 16 11月, 2005 1 次提交
  23. 14 11月, 2005 2 次提交
  24. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4