1. 19 3月, 2021 1 次提交
    • Q
      KVM: arm64: Prepare the creation of s1 mappings at EL2 · f320bc74
      Quentin Perret 提交于
      When memory protection is enabled, the EL2 code needs the ability to
      create and manage its own page-table. To do so, introduce a new set of
      hypercalls to bootstrap a memory management system at EL2.
      
      This leads to the following boot flow in nVHE Protected mode:
      
       1. the host allocates memory for the hypervisor very early on, using
          the memblock API;
      
       2. the host creates a set of stage 1 page-table for EL2, installs the
          EL2 vectors, and issues the __pkvm_init hypercall;
      
       3. during __pkvm_init, the hypervisor re-creates its stage 1 page-table
          and stores it in the memory pool provided by the host;
      
       4. the hypervisor then extends its stage 1 mappings to include a
          vmemmap in the EL2 VA space, hence allowing to use the buddy
          allocator introduced in a previous patch;
      
       5. the hypervisor jumps back in the idmap page, switches from the
          host-provided page-table to the new one, and wraps up its
          initialization by enabling the new allocator, before returning to
          the host.
      
       6. the host can free the now unused page-table created for EL2, and
          will now need to issue hypercalls to make changes to the EL2 stage 1
          mappings instead of modifying them directly.
      
      Note that for the sake of simplifying the review, this patch focuses on
      the hypervisor side of things. In other words, this only implements the
      new hypercalls, but does not make use of them from the host yet. The
      host-side changes will follow in a subsequent patch.
      
      Credits to Will for __pkvm_init_switch_pgd.
      Acked-by: NWill Deacon <will@kernel.org>
      Co-authored-by: NWill Deacon <will@kernel.org>
      Signed-off-by: NWill Deacon <will@kernel.org>
      Signed-off-by: NQuentin Perret <qperret@google.com>
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20210319100146.1149909-18-qperret@google.com
      f320bc74
  2. 10 3月, 2021 1 次提交
    • M
      KVM: arm64: Ensure I-cache isolation between vcpus of a same VM · 01dc9262
      Marc Zyngier 提交于
      It recently became apparent that the ARMv8 architecture has interesting
      rules regarding attributes being used when fetching instructions
      if the MMU is off at Stage-1.
      
      In this situation, the CPU is allowed to fetch from the PoC and
      allocate into the I-cache (unless the memory is mapped with
      the XN attribute at Stage-2).
      
      If we transpose this to vcpus sharing a single physical CPU,
      it is possible for a vcpu running with its MMU off to influence
      another vcpu running with its MMU on, as the latter is expected to
      fetch from the PoU (and self-patching code doesn't flush below that
      level).
      
      In order to solve this, reuse the vcpu-private TLB invalidation
      code to apply the same policy to the I-cache, nuking it every time
      the vcpu runs on a physical CPU that ran another vcpu of the same
      VM in the past.
      
      This involve renaming __kvm_tlb_flush_local_vmid() to
      __kvm_flush_cpu_context(), and inserting a local i-cache invalidation
      there.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      Acked-by: NWill Deacon <will@kernel.org>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Link: https://lore.kernel.org/r/20210303164505.68492-1-maz@kernel.org
      01dc9262
  3. 06 3月, 2021 1 次提交
  4. 23 1月, 2021 1 次提交
  5. 20 1月, 2021 1 次提交
  6. 17 12月, 2020 1 次提交
  7. 04 12月, 2020 3 次提交
  8. 27 11月, 2020 1 次提交
  9. 16 11月, 2020 1 次提交
    • W
      KVM: arm64: Allocate hyp vectors statically · b881cdce
      Will Deacon 提交于
      The EL2 vectors installed when a guest is running point at one of the
      following configurations for a given CPU:
      
        - Straight at __kvm_hyp_vector
        - A trampoline containing an SMC sequence to mitigate Spectre-v2 and
          then a direct branch to __kvm_hyp_vector
        - A dynamically-allocated trampoline which has an indirect branch to
          __kvm_hyp_vector
        - A dynamically-allocated trampoline containing an SMC sequence to
          mitigate Spectre-v2 and then an indirect branch to __kvm_hyp_vector
      
      The indirect branches mean that VA randomization at EL2 isn't trivially
      bypassable using Spectre-v3a (where the vector base is readable by the
      guest).
      
      Rather than populate these vectors dynamically, configure everything
      statically and use an enumerated type to identify the vector "slot"
      corresponding to one of the configurations above. This both simplifies
      the code, but also makes it much easier to implement at EL2 later on.
      Signed-off-by: NWill Deacon <will@kernel.org>
      [maz: fixed double call to kvm_init_vector_slots() on nVHE]
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      Cc: Marc Zyngier <maz@kernel.org>
      Cc: Quentin Perret <qperret@google.com>
      Link: https://lore.kernel.org/r/20201113113847.21619-8-will@kernel.org
      b881cdce
  10. 30 9月, 2020 5 次提交
  11. 29 9月, 2020 3 次提交
  12. 16 9月, 2020 5 次提交
  13. 28 8月, 2020 2 次提交
    • J
      KVM: arm64: Survive synchronous exceptions caused by AT instructions · 88a84ccc
      James Morse 提交于
      KVM doesn't expect any synchronous exceptions when executing, any such
      exception leads to a panic(). AT instructions access the guest page
      tables, and can cause a synchronous external abort to be taken.
      
      The arm-arm is unclear on what should happen if the guest has configured
      the hardware update of the access-flag, and a memory type in TCR_EL1 that
      does not support atomic operations. B2.2.6 "Possible implementation
      restrictions on using atomic instructions" from DDI0487F.a lists
      synchronous external abort as a possible behaviour of atomic instructions
      that target memory that isn't writeback cacheable, but the page table
      walker may behave differently.
      
      Make KVM robust to synchronous exceptions caused by AT instructions.
      Add a get_user() style helper for AT instructions that returns -EFAULT
      if an exception was generated.
      
      While KVM's version of the exception table mixes synchronous and
      asynchronous exceptions, only one of these can occur at each location.
      
      Re-enter the guest when the AT instructions take an exception on the
      assumption the guest will take the same exception. This isn't guaranteed
      to make forward progress, as the AT instructions may always walk the page
      tables, but guest execution may use the translation cached in the TLB.
      
      This isn't a problem, as since commit 5dcd0fdb ("KVM: arm64: Defer guest
      entry when an asynchronous exception is pending"), KVM will return to the
      host to process IRQs allowing the rest of the system to keep running.
      
      Cc: stable@vger.kernel.org # <v5.3: 5dcd0fdb ("KVM: arm64: Defer guest entry when an asynchronous exception is pending")
      Signed-off-by: NJames Morse <james.morse@arm.com>
      Reviewed-by: NMarc Zyngier <maz@kernel.org>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      88a84ccc
    • J
      KVM: arm64: Add kvm_extable for vaxorcism code · e9ee186b
      James Morse 提交于
      KVM has a one instruction window where it will allow an SError exception
      to be consumed by the hypervisor without treating it as a hypervisor bug.
      This is used to consume asynchronous external abort that were caused by
      the guest.
      
      As we are about to add another location that survives unexpected exceptions,
      generalise this code to make it behave like the host's extable.
      
      KVM's version has to be mapped to EL2 to be accessible on nVHE systems.
      
      The SError vaxorcism code is a one instruction window, so has two entries
      in the extable. Because the KVM code is copied for VHE and nVHE, we end up
      with four entries, half of which correspond with code that isn't mapped.
      Signed-off-by: NJames Morse <james.morse@arm.com>
      Reviewed-by: NMarc Zyngier <maz@kernel.org>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      e9ee186b
  14. 08 7月, 2020 1 次提交
    • M
      KVM: arm64: Don't use has_vhe() for CHOOSE_HYP_SYM() · 6de7dd31
      Marc Zyngier 提交于
      The recently introduced CHOOSE_HYP_SYM() macro picks one symbol
      or another, depending on whether the kernel run as a VHE
      hypervisor or not. For that, it uses the has_vhe() helper, which
      is itself implemented as a final capability.
      
      Unfortunately, __copy_hyp_vect_bpi now indirectly uses CHOOSE_HYP_SYM
      to get the __bp_harden_hyp_vecs symbol, using has_vhe() in the process.
      At this stage, the capability isn't final and things explode:
      
      [    0.000000] ACPI: SRAT not present
      [    0.000000] percpu: Embedded 34 pages/cpu s101264 r8192 d29808 u139264
      [    0.000000] Detected PIPT I-cache on CPU0
      [    0.000000] ------------[ cut here ]------------
      [    0.000000] kernel BUG at arch/arm64/include/asm/cpufeature.h:459!
      [    0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
      [    0.000000] Modules linked in:
      [    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.8.0-rc4-00080-gd630681366e5 #1388
      [    0.000000] pstate: 80000085 (Nzcv daIf -PAN -UAO BTYPE=--)
      [    0.000000] pc : check_branch_predictor+0x3a4/0x408
      [    0.000000] lr : check_branch_predictor+0x2a4/0x408
      [    0.000000] sp : ffff800011693e90
      [    0.000000] x29: ffff800011693e90 x28: ffff8000116a1530
      [    0.000000] x27: ffff8000112c1008 x26: ffff800010ca6ff8
      [    0.000000] x25: ffff8000112c1000 x24: ffff8000116a1320
      [    0.000000] x23: 0000000000000000 x22: ffff8000112c1000
      [    0.000000] x21: ffff800010177120 x20: ffff8000116ae108
      [    0.000000] x19: 0000000000000000 x18: ffff800011965c90
      [    0.000000] x17: 0000000000022000 x16: 0000000000000003
      [    0.000000] x15: 00000000ffffffff x14: ffff8000118c3a38
      [    0.000000] x13: 0000000000000021 x12: 0000000000000022
      [    0.000000] x11: d37a6f4de9bd37a7 x10: 000000000000001d
      [    0.000000] x9 : 0000000000000000 x8 : ffff800011f8dad8
      [    0.000000] x7 : ffff800011965ad0 x6 : 0000000000000003
      [    0.000000] x5 : 0000000000000000 x4 : 0000000000000000
      [    0.000000] x3 : 0000000000000100 x2 : 0000000000000004
      [    0.000000] x1 : ffff8000116ae148 x0 : 0000000000000000
      [    0.000000] Call trace:
      [    0.000000]  check_branch_predictor+0x3a4/0x408
      [    0.000000]  update_cpu_capabilities+0x84/0x138
      [    0.000000]  init_cpu_features+0x2c0/0x2d8
      [    0.000000]  cpuinfo_store_boot_cpu+0x54/0x64
      [    0.000000]  smp_prepare_boot_cpu+0x2c/0x60
      [    0.000000]  start_kernel+0x16c/0x574
      [    0.000000] Code: 17ffffc7 91010281 14000198 17ffffca (d4210000)
      
      This is addressed using a two-fold process:
      - Replace has_vhe() with is_kernel_in_hyp_mode(), which tests
        whether we are running at EL2.
      - Make CHOOSE_HYP_SYM() return an *undefined* symbol when
        compiled in the nVHE hypervisor, as we really should never
        use this helper in the nVHE-specific code.
      
      With this in place, we're back to a bootable kernel again.
      
      Fixes: b877e984 ("KVM: arm64: Build hyp-entry.S separately for VHE/nVHE")
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      6de7dd31
  15. 07 7月, 2020 2 次提交
  16. 06 7月, 2020 5 次提交
  17. 11 6月, 2020 1 次提交
  18. 09 6月, 2020 1 次提交
  19. 25 5月, 2020 1 次提交
  20. 16 5月, 2020 1 次提交
  21. 10 3月, 2020 1 次提交
    • M
      arm64: kvm: Modernize __smccc_workaround_1_smc_start annotations · 4db61fef
      Mark Brown 提交于
      In an effort to clarify and simplify the annotation of assembly functions
      in the kernel new macros have been introduced. These replace ENTRY and
      ENDPROC with separate annotations for standard C callable functions,
      data and code with different calling conventions.
      
      Using these for __smccc_workaround_1_smc is more involved than for most
      symbols as this symbol is annotated quite unusually, rather than just have
      the explicit symbol we define _start and _end symbols which we then use to
      compute the length. This does not play at all nicely with the new style
      macros. Instead define a constant for the size of the function and use that
      in both the C code and for .org based size checks in the assembly code.
      Signed-off-by: NMark Brown <broonie@kernel.org>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: NMarc Zyngier <maz@kernel.org>
      4db61fef
  22. 05 7月, 2019 1 次提交
    • J
      KVM: arm64: Consume pending SError as early as possible · 0e5b9c08
      James Morse 提交于
      On systems with v8.2 we switch the 'vaxorcism' of guest SError with an
      alternative sequence that uses the ESB-instruction, then reads DISR_EL1.
      This saves the unmasking and remasking of asynchronous exceptions.
      
      We do this after we've saved the guest registers and restored the
      host's. Any SError that becomes pending due to this will be accounted
      to the guest, when it actually occurred during host-execution.
      
      Move the ESB-instruction as early as possible. Any guest SError
      will become pending due to this ESB-instruction and then consumed to
      DISR_EL1 before the host touches anything.
      
      This lets us account for host/guest SError precisely on the guest
      exit exception boundary.
      
      Because the ESB-instruction now lands in the preamble section of
      the vectors, we need to add it to the unpatched indirect vectors
      too, and to any sequence that may be patched in over the top.
      
      The ESB-instruction always lives in the head of the vectors,
      to be before any memory write. Whereas the register-store always
      lives in the tail.
      Signed-off-by: NJames Morse <james.morse@arm.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      0e5b9c08