1. 30 11月, 2020 5 次提交
  2. 22 9月, 2020 8 次提交
  3. 25 7月, 2020 2 次提交
  4. 19 5月, 2020 5 次提交
  5. 21 11月, 2019 5 次提交
  6. 05 9月, 2019 6 次提交
  7. 01 7月, 2019 1 次提交
  8. 25 5月, 2019 1 次提交
    • O
      uapi/habanalabs: add opcode for enable/disable device debug mode · 2add64eb
      Oded Gabbay 提交于
      This patch defines a new opcode in the DEBUG IOCTL that is used by the
      user to notify the driver when the user wants to start or stop using the
      debug and profile infrastructure of the device. i.e. set the device to
      debug mode or to non-debug mode.
      
      There are a couple of restrictions that this new opcode introduces:
      
      1. The user can't configure the debug/profiling infrastructure before he
         sets the device to debug mode, by using this new opcode.
      
      2. The user can't set the device to debug mode unless he is the only user
         that is currently using (has an open FD) the device.
      
      3. Other users can't use the device (open a new FD) in case an existing
         user has set the device into debug mode.
      
      These restrictions are needed because the debug and profiling
      infrastructure is a shared component in the ASIC and therefore, can't be
      used while multiple users are working on the device.
      
      Because the driver currently does NOT support multiple users, the
      implementation of the restrictions is not required at this point. However,
      the interface definition is needed in order to avoid changing the user API
      later on.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      2add64eb
  9. 21 4月, 2019 1 次提交
  10. 03 4月, 2019 1 次提交
  11. 02 4月, 2019 1 次提交
    • O
      habanalabs: add new IOCTL for debug, tracing and profiling · 315bc055
      Omer Shpigelman 提交于
      Habanalabs ASICs use the ARM coresight infrastructure to support debug,
      tracing and profiling of neural networks topologies.
      
      Because the coresight is configured using register writes and reads, and
      some of the registers hold sensitive information (e.g. the address in
      the device's DRAM where the trace data is written to), the user must go
      through the kernel driver to configure this mechanism.
      
      This patch implements the common code of the IOCTL and calls the
      ASIC-specific function for the actual H/W configuration.
      
      The IOCTL supports configuration of seven coresight components:
      ETR, ETF, STM, FUNNEL, BMON, SPMU and TIMESTAMP
      
      The user specifies which component he wishes to configure and provides a
      pointer to a structure (located in its process space) that contains the
      relevant configuration.
      
      The common code copies the relevant data from the user-space to kernel
      space and then calls the ASIC-specific function to do the H/W
      configuration.
      
      After the configuration is done, which is usually composed
      of several IOCTL calls depending on what the user wanted to trace, the
      user can start executing the topology. The trace data will be written to
      the user's area in the device's DRAM.
      
      After the tracing operation is complete, and user will call the IOCTL
      again to disable the tracing operation. The user also need to read
      values from registers for some of the components (e.g. the size of the
      trace data in the device's DRAM). In that case, the user will provide a
      pointer to an "output" structure in user-space, which the IOCTL code will
      fill according the to selected component.
      Signed-off-by: NOmer Shpigelman <oshpigelman@habana.ai>
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      315bc055
  12. 24 3月, 2019 1 次提交
  13. 28 2月, 2019 1 次提交
  14. 27 2月, 2019 1 次提交
    • O
      habanalabs: allow memory allocations larger than 4GB · 230afe74
      Oded Gabbay 提交于
      This patch increase the size field in the uapi structure of the Memory
      IOCTL from 32-bit to 64-bit. This is to allow the user to allocate and/or
      map memory in chunks that are larger then 4GB.
      
      Goya's device memory (DRAM) can be up to 16GB, and for certain
      topologies, the user may want an allocation that is larger than 4GB.
      
      This change doesn't break current user-space because there was a "pad"
      field in the uapi structure right after the size field. Changing the size
      field to be 64-bit and removing the pad field maintains compatibility with
      current user-space.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      230afe74
  15. 07 3月, 2019 1 次提交