1. 26 10月, 2018 1 次提交
  2. 23 10月, 2018 2 次提交
  3. 22 10月, 2018 1 次提交
  4. 20 10月, 2018 1 次提交
  5. 19 10月, 2018 3 次提交
  6. 17 10月, 2018 2 次提交
  7. 16 10月, 2018 2 次提交
    • M
      FDDI: defza: Add support for DEC FDDIcontroller 700 TURBOchannel adapter · 61414f5e
      Maciej W. Rozycki 提交于
      Add support for the DEC FDDIcontroller 700 (DEFZA), Digital Equipment
      Corporation's first-generation FDDI network interface adapter, made for
      TURBOchannel and based on a discrete version of what eventually became
      Motorola's widely used CAMEL chipset.
      
      The CAMEL chipset is present for example in the DEC FDDIcontroller
      TURBOchannel, EISA and PCI adapters (DEFTA/DEFEA/DEFPA) that we support
      with the `defxx' driver, however the host bus interface logic and the
      firmware API are different in the DEFZA and hence a separate driver is
      required.
      
      There isn't much to say about the driver except that it works, but there
      is one peculiarity to mention.  The adapter implements two Tx/Rx queue
      pairs.
      
      Of these one pair is the usual network Tx/Rx queue pair, in this case
      used by the adapter to exchange frames with the ring, via the RMC (Ring
      Memory Controller) chip.  The Tx queue is handled directly by the RMC
      chip and resides in onboard packet memory.  The Rx queue is maintained
      via DMA in host memory by adapter's firmware copying received data
      stored by the RMC in onboard packet memory.
      
      The other pair is used to communicate SMT frames with adapter's
      firmware.  Any SMT frame received from the RMC via the Rx queue must be
      queued back by the driver to the SMT Rx queue for the firmware to
      process.  Similarly the firmware uses the SMT Tx queue to supply the
      driver with SMT frames that must be queued back to the Tx queue for the
      RMC to send to the ring.
      
      This solution was chosen because the designers ran out of PCB space and
      could not squeeze in more logic onto the board that would be required to
      handle this SMT frame traffic without the need to involve the driver, as
      with the later DEFTA/DEFEA/DEFPA adapters.
      
      Finally the driver does some Frame Control byte decoding, so to avoid
      magic numbers some macros are added to <linux/if_fddi.h>.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      61414f5e
    • D
      bpf, doc: add maintainers entry to related files · eea0d2ad
      Daniel Borkmann 提交于
      Add a MAINTAINERS entry to the skmsg and related files such that
      patches, features, bug reports land with the right Cc.
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      Signed-off-by: NJohn Fastabend <john.fastabend@gmail.com>
      Signed-off-by: NAlexei Starovoitov <ast@kernel.org>
      eea0d2ad
  8. 12 10月, 2018 2 次提交
  9. 11 10月, 2018 2 次提交
  10. 10 10月, 2018 3 次提交
  11. 09 10月, 2018 1 次提交
  12. 08 10月, 2018 1 次提交
    • M
      mmc: uniphier-sd: add UniPhier SD/eMMC controller driver · 3fd784f7
      Masahiro Yamada 提交于
      Here is another TMIO MMC variant found in Socionext UniPhier SoCs.
      
      As commit b6147490 ("mmc: tmio: split core functionality, DMA and
      MFD glue") said, these MMC controllers use the IP from Panasonic.
      
      However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip
      was the first upstreamed user of this IP.  The common driver code
      for this IP is now called 'tmio-mmc-core' in Linux although it is a
      historical misnomer.
      
      Anyway, this driver select's MMC_TMIO_CORE to borrow the common code
      from tmio-mmc-core.c
      
      Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine
      like renesas_sdhi_sys_dmac.c.  The difference is UniPhier SoCs use a
      single DMA channel whereas Renesas chips request separate channels for
      RX and TX.
      
      Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine
      like renesas_sdhi_internal_dmac.c  The register map is almost the same,
      so I guess Renesas and Socionext use the same internal DMA hardware.
      The main difference is, the register offsets are doubled for Renesas.
      
                              Renesas      Socionext
                              SDHI         UniPhier
        DM_CM_DTRAN_MODE      0x820        0x410
        DM_CM_DTRAN_CTRL      0x828        0x414
        DM_CM_RST             0x830        0x418
        DM_CM_INFO1           0x840        0x420
        DM_CM_INFO1_MASK      0x848        0x424
        DM_CM_INFO2           0x850        0x428
        DM_CM_INFO2_MASK      0x858        0x42c
        DM_DTRAN_ADDR         0x880        0x440
        DM_DTRAN_ADDREX        ---         0x444
      
      This comes from the difference of host->bus_shift; 2 for Renesas SoCs,
      and 1 for UniPhier SoCs.  Also, the datasheet for UniPhier SoCs defines
      DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers.
      
      It could be possible to factor out the DMA common code by introducing
      some hooks to cope with platform quirks, but this patch does not touch
      that for now.
      Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      3fd784f7
  13. 06 10月, 2018 1 次提交
  14. 04 10月, 2018 1 次提交
  15. 03 10月, 2018 2 次提交
  16. 02 10月, 2018 2 次提交
  17. 30 9月, 2018 1 次提交
  18. 29 9月, 2018 3 次提交
  19. 28 9月, 2018 1 次提交
  20. 27 9月, 2018 2 次提交
  21. 23 9月, 2018 1 次提交
  22. 21 9月, 2018 4 次提交
  23. 19 9月, 2018 1 次提交