1. 19 7月, 2018 1 次提交
    • F
      net/mlx5: FW tracer, add hardware structures · eff8ea8f
      Feras Daoud 提交于
      This change adds the infrastructure to mlx5 core fw tracer.
      It introduces the following 4 new registers:
      MLX5_REG_MTRC_CAP  - Used to read tracer capabilities
      MLX5_REG_MTRC_CONF - Used to set tracer configurations
      MLX5_REG_MTRC_STDB - Used to query tracer strings database
      MLX5_REG_MTRC_CTRL - Used to control the tracer
      
      The capability of the tracing can be checked using mcam access
      register, therefore, the mcam access register interface will expose
      the tracer register.
      Signed-off-by: NFeras Daoud <ferasda@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      eff8ea8f
  2. 05 7月, 2018 1 次提交
  3. 22 6月, 2018 1 次提交
  4. 20 6月, 2018 1 次提交
  5. 01 6月, 2018 2 次提交
  6. 30 5月, 2018 1 次提交
  7. 26 5月, 2018 1 次提交
  8. 25 5月, 2018 2 次提交
  9. 18 5月, 2018 3 次提交
  10. 17 5月, 2018 2 次提交
  11. 01 5月, 2018 1 次提交
    • I
      net/mlx5: Accel, Add TLS tx offload interface · 1ae17322
      Ilya Lesokhin 提交于
      Add routines for manipulating TLS TX offload contexts.
      
      In Innova TLS, TLS contexts are added or deleted
      via a command message over the SBU connection.
      The HW then sends a response message over the same connection.
      
      Add implementation for Innova TLS (FPGA-based) hardware.
      
      These routines will be used by the TLS offload support in a later patch
      
      mlx5/accel is a middle acceleration layer to allow mlx5e and other ULPs
      to work directly with mlx5_core rather than Innova FPGA or other mlx5
      acceleration providers.
      
      In the future, when IPSec/TLS or any other acceleration gets integrated
      into ConnectX chip, mlx5/accel layer will provide the integrated
      acceleration, rather than the Innova one.
      Signed-off-by: NIlya Lesokhin <ilyal@mellanox.com>
      Signed-off-by: NBoris Pismenny <borisp@mellanox.com>
      Acked-by: NSaeed Mahameed <saeedm@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1ae17322
  12. 06 4月, 2018 3 次提交
  13. 31 3月, 2018 1 次提交
    • T
      net/mlx5e: Use linear SKB in Striding RQ · 619a8f2a
      Tariq Toukan 提交于
      Current Striding RQ HW feature utilizes the RX buffers so that
      there is no wasted room between the strides. This maximises
      the memory utilization.
      This prevents the use of build_skb() (which requires headroom
      and tailroom), and demands to memcpy the packets headers into
      the skb linear part.
      
      In this patch, whenever a set of conditions holds, we apply
      an RQ configuration that allows combining the use of linear SKB
      on top of a Striding RQ.
      
      To use build_skb() with Striding RQ, the following must hold:
      1. packet does not cross a page boundary.
      2. there is enough headroom and tailroom surrounding the packet.
      
      We can satisfy 1 and 2 by configuring:
      	stride size = MTU + headroom + tailoom.
      
      This is possible only when:
      a. (MTU - headroom - tailoom) does not exceed PAGE_SIZE.
      b. HW LRO is turned off.
      
      Using linear SKB has many advantages:
      - Saves a memcpy of the headers.
      - No page-boundary checks in datapath.
      - No filler CQEs.
      - Significantly smaller CQ.
      - SKB data continuously resides in linear part, and not split to
        small amount (linear part) and large amount (fragment).
        This saves datapath cycles in driver and improves utilization
        of SKB fragments in GRO.
      - The fragments of a resulting GRO SKB follow the IP forwarding
        assumption of equal-size fragments.
      
      Some implementation details:
      HW writes the packets to the beginning of a stride,
      i.e. does not keep headroom. To overcome this we make sure we can
      extend backwards and use the last bytes of stride i-1.
      Extra care is needed for stride 0 as it has no preceding stride.
      We make sure headroom bytes are available by shifting the buffer
      pointer passed to HW by headroom bytes.
      
      This configuration now becomes default, whenever capable.
      Of course, this implies turning LRO off.
      
      Performance testing:
      ConnectX-5, single core, single RX ring, default MTU.
      
      UDP packet rate, early drop in TC layer:
      
      --------------------------------------------
      | pkt size | before    | after     | ratio |
      --------------------------------------------
      | 1500byte | 4.65 Mpps | 5.96 Mpps | 1.28x |
      |  500byte | 5.23 Mpps | 5.97 Mpps | 1.14x |
      |   64byte | 5.94 Mpps | 5.96 Mpps | 1.00x |
      --------------------------------------------
      
      TCP streams: ~20% gain
      Signed-off-by: NTariq Toukan <tariqt@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      619a8f2a
  14. 28 3月, 2018 1 次提交
  15. 27 3月, 2018 6 次提交
  16. 20 3月, 2018 1 次提交
    • B
      net/mlx5: Packet pacing enhancement · 05d3ac97
      Bodong Wang 提交于
      Add two new parameters: max_burst_sz and typical_pkt_size (both
      in bytes) to rate limit configurations.
      
      max_burst_sz: The device will schedule bursts of packets for an
      SQ connected to this rate, smaller than or equal to this value.
      Value 0x0 indicates packet bursts will be limited to the device
      defaults. This field should be used if bursts of packets must be
      strictly kept under a certain value.
      
      typical_pkt_size: When the rate limit is intended for a stream of
      similar packets, stating the typical packet size can improve the
      accuracy of the rate limiter. The expected packet size will be
      the same for all SQs associated with the same rate limit index.
      
      Ethernet driver is updated according to this change, but these two
      parameters will be kept as 0 due to lacking of proper way to get the
      configurations from user space which requires to change
      ndo_set_tx_maxrate interface.
      Signed-off-by: NBodong Wang <bodong@mellanox.com>
      Reviewed-by: NDaniel Jurgens <danielj@mellanox.com>
      Reviewed-by: NYishai Hadas <yishaih@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      05d3ac97
  17. 07 3月, 2018 2 次提交
  18. 20 1月, 2018 1 次提交
  19. 18 1月, 2018 1 次提交
  20. 12 1月, 2018 1 次提交
    • E
      {net,ib}/mlx5: Don't disable local loopback multicast traffic when needed · 8978cc92
      Eran Ben Elisha 提交于
      There are systems platform information management interfaces (such as
      HOST2BMC) for which we cannot disable local loopback multicast traffic.
      
      Separate disable_local_lb_mc and disable_local_lb_uc capability bits so
      driver will not disable multicast loopback traffic if not supported.
      (It is expected that Firmware will not set disable_local_lb_mc if
      HOST2BMC is running for example.)
      
      Function mlx5_nic_vport_update_local_lb will do best effort to
      disable/enable UC/MC loopback traffic and return success only in case it
      succeeded to changed all allowed by Firmware.
      
      Adapt mlx5_ib and mlx5e to support the new cap bits.
      
      Fixes: 2c43c5a0 ("net/mlx5e: Enable local loopback in loopback selftest")
      Fixes: c85023e1 ("IB/mlx5: Add raw ethernet local loopback support")
      Fixes: bded747b ("net/mlx5: Add raw ethernet local loopback firmware command")
      Signed-off-by: NEran Ben Elisha <eranbe@mellanox.com>
      Cc: kernel-team@fb.com
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      8978cc92
  21. 09 1月, 2018 3 次提交
    • O
      net/mlx5: Add hairpin definitions to the FW API · 40817cdb
      Or Gerlitz 提交于
      Add hairpin definitions to the IFC file.
      
      This includes the HCA ID, few HCA hairpin capabilities, new
      fields in RQ/SQ used later for the pairing and the WQ hairpin
      data size attribute.
      Signed-off-by: NOr Gerlitz <ogerlitz@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      40817cdb
    • D
      {net, IB}/mlx5: Manage port association for multiport RoCE · 32f69e4b
      Daniel Jurgens 提交于
      When mlx5_ib_add is called determine if the mlx5 core device being
      added is capable of dual port RoCE operation. If it is, determine
      whether it is a master device or a slave device using the
      num_vhca_ports and affiliate_nic_vport_criteria capabilities.
      
      If the device is a slave, attempt to find a master device to affiliate it
      with. Devices that can be affiliated will share a system image guid. If
      none are found place it on a list of unaffiliated ports. If a master is
      found bind the port to it by configuring the port affiliation in the NIC
      vport context.
      
      Similarly when mlx5_ib_remove is called determine the port type. If it's
      a slave port, unaffiliate it from the master device, otherwise just
      remove it from the unaffiliated port list.
      
      The IB device is registered as a multiport device, even if a 2nd port is
      not available for affiliation. When the 2nd port is affiliated later the
      GID cache must be refreshed in order to get the default GIDs for the 2nd
      port in the cache. Export roce_rescan_device to provide a mechanism to
      refresh the cache after a new port is bound.
      
      In a multiport configuration all IB object (QP, MR, PD, etc) related
      commands should flow through the master mlx5_core_dev, other commands
      must be sent to the slave port mlx5_core_mdev, an interface is provide
      to get the correct mdev for non IB object commands.
      Signed-off-by: NDaniel Jurgens <danielj@mellanox.com>
      Reviewed-by: NParav Pandit <parav@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leon@kernel.org>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      32f69e4b
    • D
      net/mlx5: Set software owner ID during init HCA · 8737f818
      Daniel Jurgens 提交于
      Generate a unique 128bit identifier for each host and pass that value to
      firmware in the INIT_HCA command if it reports the sw_owner_id
      capability. Each device bound to the mlx5_core driver will have the same
      software owner ID.
      
      In subsequent patches mlx5_core devices will be bound via a new VPort
      command so that they can operate together under a single InfiniBand
      device. Only devices that have the same software owner ID can be bound,
      to prevent traffic intended for one host arriving at another.
      
      The INIT_HCA command length was expanded by 128 bits. The command
      length is provided as an input FW commands. Older FW does not have a
      problem receiving this command in the new longer form.
      Signed-off-by: NDaniel Jurgens <danielj@mellanox.com>
      Reviewed-by: NParav Pandit <parav@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leon@kernel.org>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      8737f818
  22. 20 12月, 2017 1 次提交
  23. 05 11月, 2017 2 次提交
  24. 26 10月, 2017 1 次提交