Add bits and pieces needed to support IP block variant found on
i.MX8MQ SoCs.

Cc: p.zabel@pengutronix.de
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
[p.zabel@pengutronix.de: fixed whitespace alignment]
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Add support for resetting blocks through the Linux reset controller
subsystem when reset lines are provided through a SW_INIT-style reset
controller on Broadcom STB SoCs.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This driver works for controlling the reset lines including USB3
glue layer, however, this can be applied to other glue layers.
Now this patch renames the driver from "reset-uniphier-usb3" to
"reset-uniphier-glue".

At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to
CONFIG_RESET_UNIPHIER_GLUE.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.

We do not need this early reset driver for Stratix10, because on
arm64, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer. Thus, we use
a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform.
The Stratix10 platform will continue to use the reset-simple platform
driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>
[p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple]
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Add reset controller for SDM845 SoCs to control reset signals provided
by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
Audio, SP and APPS
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The Amlogic Audio ARB is a simple device which enables or
disables the access of Audio FIFOs to DDR on AXG based SoC.
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Add a reset line to enable USB3 core implemented in UniPhier SoCs.

This reuses only the reset operations in reset-simple, because
the reset-simple doesn't handle any SoC-dependent clocks and resets.
This reset line is included in the USB3 glue layer, and it's necessary
to enable clocks and deassert resets of the layer before using this
reset line.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
	activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register	has no effect
Writing '1' on reset CLEAR register
	releases the reset of the corresponding peripheral

See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This config select's MFD_SYSCON, but does not depend on HAS_IOMEM.

Compile testing on architecture without HAS_IOMEM causes "unmet
direct dependencies" in Kconfig phase.

Detected by "make ARCH=score allyesconfig".
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

ASPEED BMC SoCs have a reset controller in the LPC IP that can be
controlled using this driver to release the UARTs from reset.

No special configuration is required, so only the compatible string is
added.
Signed-off-by: NJoel Stanley <joel@jms.id.au>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The reset-simple driver can be used without changes.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NAlexandru Gagniuc <alex.g@adaptrum.com>

The reset-simple driver can be used without changes.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NGabriel Fernandez <gabriel.fernandez@st.com>

Add reset line status readback, inverted status support, and socfpga
device tree quirks to the simple reset driver, and use it to replace
the socfpga driver.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Use the newly created copies in the reset-simple driver to replace the
sunxi platform driver code and reset operations. The separate sunxi
driver still remains to register the early reset controllers, but it
reuses the reset operations in reset-simple.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NAlexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>

Copy reusable parts from the sunxi driver, to add a driver for simple
reset controllers with reset lines that can be controlled by toggling
bits in exclusive, contiguous register ranges using read-modify-write
cycles under a spinlock.

The following patches will replace compatible reset drivers with
reset-simple, extending it where necessary.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NAlexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>

Enable the reset driver to get built for the Stratix10 platform.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The HSDK reset driver is only useful when building for an ARC HSDK
platform.

While at it, drop the "default n", as that is the default.

Fixes: e0be864f ("ARC: reset: introduce HSDKv1 reset driver")
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
[p.zabel@pengutronix.de: rebased, renamed RESET_HSDK_V1 to RESET_HSDK]
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

ARC AXS10x boards support custom IP-block which allows to control
reset signals of selected peripherals. For example DW GMAC, etc...
This block is controlled via memory-mapped register (AKA CREG) which
represents up-to 32 reset lines. This regiter is self-clearing so we
don't need to deassert line after reset.

As of today only the following lines are used:
 - DW GMAC - line 5
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

There is no plan yet to do a v2 board. And even if we were to do it only
some IPs would actually change, so it be best to add suffixes at that
point, not now !
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This avoids the error:
drivers/reset/reset-hsdk-v1.o: In function `hsdkv1_reset_probe':
/home/thomas/git/linux/drivers/reset/reset-hsdk-v1.c:101: undefined
reference to `devm_ioremap_resource'
collect2: error: ld returned 1 exit status
Signed-off-by: NThomas Meyer <thomas@m3y3r.de>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.

For some devices the request and the status bits are different.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Cc: john@phrozen.org
Cc: kishon@ti.com
Cc: mark.rutland@arm.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17125/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This reverts commit 2acb037f.

We ended up merging the reset controller into the clock
controller so we can now get rid of this stand-alone
implementation.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.

The list of available reset lines is documented in the DT bindings.
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Some TI Keystone family of SoCs contain a system controller (like the
Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations
are provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management
of various devices present on the SoC. Various reset functionalities
are achieved by the means of different TI SCI device operations
provided by the TI SCI framework.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
[s-anna@ti.com: documentation changes, revised commit message]
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
[p.zabel@pengutronix.de: const struct reset_control_ops]
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The Cortina Systems Gemini reset controller is a simple
32bit register with self-deasserting reset lines. It is
accessed using regmap over syscon.
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Rename the current Kconfig name used for the TI SYSCON Reset
driver from TI_SYSCON_RESET to RESET_TI_SYSCON to match the
convention used for all the reset drivers present at the
base reset folder.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This patch adds the reset controller functionality for
Peripheral PHYs to the Arria10 System Resource Chip.
Signed-off-by: NThor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Add reset controller driver exposing various reset faculties,
implemented by System Reset Controller IP block.

Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This patch adds reset controller driver for ZTE's zx2967 family.
Signed-off-by: NBaoyou Xie <baoyou.xie@linaro.org>
Reviewed-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This driver uses the services provided by the BPMP firmware driver to
implement a reset driver based on the MRQ_RESET request.
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Acked-by: NJames Hartley <james.hartley@imgtec.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: NJoachim Eastwood <manabian@gmail.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.
Acked-by: NAban Bedel <albeu@free.fr>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>