1. 19 12月, 2013 1 次提交
  2. 15 11月, 2013 1 次提交
  3. 26 9月, 2013 1 次提交
  4. 24 9月, 2013 1 次提交
  5. 27 8月, 2013 2 次提交
  6. 23 8月, 2013 5 次提交
    • Z
      PCI: Disable decoding for BAR sizing only when it was actually enabled · 808e34e2
      Zoltan Kiss 提交于
      We disable BARs while sizing them so we don't cause conflicts with other
      devices (see 253d2e54 and bbffe435).  But if device decoding is already
      disabled before we size the BAR, we don't need to disable it again.
      
      [bhelgaas: changelog, add PCI_COMMAND_DECODING_ENABLE for readability]
      Signed-off-by: NZoltan Kiss <zoltan.kiss@citrix.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      808e34e2
    • Y
      PCI: Don't restrict MPS for slots below Root Ports · d4aa68f6
      Yijing Wang 提交于
      When booting with "pci=pcie_bus_safe", we previously limited the
      fabric MPS to 128 when we found:
      
        (1) A hotplug-capable Downstream Port ("dev->is_hotplug_bridge &&
            pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT"), or
      
        (2) A hotplug-capable Root Port with a slot that was either empty or
            contained a multi-function device ("dev->is_hotplug_bridge &&
            !list_is_singular(&dev->bus->devices)")
      
      Part (1) is valid, but part (2) is not.
      
      After a hot-add in the slot below a Root Port, we can reconfigure all
      MPS values in the fabric below the Root Port because the new device is
      the only thing below the Root Port and there are no active drivers.
      Therefore, there's no reason to limit the MPS for Root Ports, no
      matter what's in the slot.
      
      Test info:
      
          -+-[0000:40]-+-07.0-[0000:46]--+-00.0  Intel 82576 NIC
                                         \-00.1  Intel 82576 NIC
      
          0000:40:07.0 Root Port bridge to [bus 46] (MPS supported=256)
          0000:46:00.0 Endpoint                     (MPS supported=512)
          0000:46:00.1 Endpoint                     (MPS supported=512)
      
          # echo 0 > /sys/bus/pci/slots/7/power
          # echo 1 > /sys/bus/pci/slots/7/power
          pcieport 0000:40:07.0: PCI-E Max Payload Size set to 256/ 256 (was 256)
          pci 0000:46:00.0:      PCI-E Max Payload Size set to 256/ 512 (was 128)
          pci 0000:46:00.1:      PCI-E Max Payload Size set to 256/ 512 (was 128)
      
      Before this change, we set MPS to 128 for the Root Port and both NICs
      because the slot contained a multi-function device and
      
          dev->is_hotplug_bridge && !list_is_singular(&dev->bus->devices)
      
      was true.  After this change, we set it to 256.
      
      [bhelgaas: changelog, comments, split out upstream bridge check]
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Jon Mason <jdmason@kudzu.us>
      d4aa68f6
    • B
      PCI: Simplify MPS test for Downstream Port · c2996948
      Bjorn Helgaas 提交于
      PCIe hotplug bridges are always either Root Ports or Downstream Ports.  No
      other device type can have a PCIe link leading downstream to a slot.
      
      Root Ports don't have an upstream bridge, so "dev->is_hotplug_bridge &&
      dev->bus->self" is true if and only if "dev" is a Downstream Port.  That
      means we can simplify this by looking at the type of "dev" itself, without
      looking upstream at all.
      
      No functional change.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      c2996948
    • B
      PCI: Simplify pcie_bus_configure_settings() interface · a58674ff
      Bjorn Helgaas 提交于
      Based on a patch by Jon Mason (see URL below).
      
      All users of pcie_bus_configure_settings() pass arguments of the form
      "bus, bus->self->pcie_mpss".  The "mpss" argument is redundant since we
      can easily look it up internally.  In addition, all callers check
      "bus->self" for NULL, which we can also do internally.
      
      This patch simplifies the interface and the callers.  No functional change.
      
      Reference: http://lkml.kernel.org/r/1317048850-30728-2-git-send-email-mason@myri.comSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
      a58674ff
    • B
      PCI: Drop "PCI-E" prefix from Max Payload Size message · 2c25e34c
      Bjorn Helgaas 提交于
      The conventional spelling is "PCIe", but I think even that is superfluous,
      so remove the whole thing.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      2c25e34c
  7. 12 8月, 2013 1 次提交
  8. 31 7月, 2013 1 次提交
  9. 26 7月, 2013 2 次提交
  10. 27 6月, 2013 1 次提交
  11. 15 6月, 2013 1 次提交
  12. 08 6月, 2013 2 次提交
  13. 06 6月, 2013 1 次提交
    • G
      PCI: Convert alloc_pci_dev(void) to pci_alloc_dev(bus) · 8b1fce04
      Gu Zheng 提交于
      Use the new pci_alloc_dev(bus) to replace the existing using of
      alloc_pci_dev(void).
      
      [bhelgaas: drop pci_bus ref later in pci_release_dev()]
      Signed-off-by: NGu Zheng <guz.fnst@cn.fujitsu.com>
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: David Airlie <airlied@linux.ie>
      Cc: Neela Syam Kolli <megaraidlinux@lsi.com>
      Cc: "James E.J. Bottomley" <JBottomley@parallels.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      8b1fce04
  14. 05 6月, 2013 1 次提交
  15. 28 5月, 2013 1 次提交
  16. 26 5月, 2013 3 次提交
  17. 08 5月, 2013 1 次提交
  18. 18 4月, 2013 1 次提交
  19. 13 4月, 2013 2 次提交
    • J
      PCI: Add pcibios hooks for adding and removing PCI buses · 10a95747
      Jiang Liu 提交于
      On ACPI-based platforms, the pci_slot driver creates PCI slot devices
      according to information from ACPI tables by registering an ACPI PCI
      subdriver.  The ACPI PCI subdriver will only be called when creating/
      destroying PCI root buses, and it won't be called when hot-plugging
      P2P bridges.  It may cause stale PCI slot devices after hot-removing
      a P2P bridge if that bridge has associated PCI slots.  And the acpiphp
      driver has the same issue too.
      
      This patch introduces two hook points into the PCI core, which will
      be invoked when creating/destroying PCI buses for PCI host and P2P
      bridges.  They could be used to setup/destroy platform dependent stuff
      in a unified way, both at boot time and for PCI hotplug operations.
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NYinghai Lu <yinghai@kernel.org>
      Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
      Cc: Toshi Kani <toshi.kani@hp.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Fenghua Yu <fenghua.yu@intel.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Myron Stowe <myron.stowe@redhat.com>
      10a95747
    • J
      PCI: Clean up usages of pci_bus->is_added · 981cf9ea
      Jiang Liu 提交于
      Now pci_bus->is_added is only used to guard invoking of
      pcibios_fixup_bus() in pci_scan_child_bus(), so just set
      it directly after the fixups and remove the other test
      and set in pci_bus_add_devices().
      
      [bhelgaas: changelog]
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NYinghai Lu <yinghai@kernel.org>
      981cf9ea
  20. 26 1月, 2013 5 次提交
  21. 14 1月, 2013 1 次提交
    • R
      ACPI / PCI: Set root bridge ACPI handle in advance · 6c0cc950
      Rafael J. Wysocki 提交于
      The ACPI handles of PCI root bridges need to be known to
      acpi_bind_one(), so that it can create the appropriate
      "firmware_node" and "physical_node" files for them, but currently
      the way it gets to know those handles is not exactly straightforward
      (to put it lightly).
      
      This is how it works, roughly:
      
        1. acpi_bus_scan() finds the handle of a PCI root bridge,
           creates a struct acpi_device object for it and passes that
           object to acpi_pci_root_add().
      
        2. acpi_pci_root_add() creates a struct acpi_pci_root object,
           populates its "device" field with its argument's address
           (device->handle is the ACPI handle found in step 1).
      
        3. The struct acpi_pci_root object created in step 2 is passed
           to pci_acpi_scan_root() and used to get resources that are
           passed to pci_create_root_bus().
      
        4. pci_create_root_bus() creates a struct pci_host_bridge object
           and passes its "dev" member to device_register().
      
        5. platform_notify(), which for systems with ACPI is set to
           acpi_platform_notify(), is called.
      
      So far, so good.  Now it starts to be "interesting".
      
        6. acpi_find_bridge_device() is used to find the ACPI handle of
           the given device (which is the PCI root bridge) and executes
           acpi_pci_find_root_bridge(), among other things, for the
           given device object.
      
        7. acpi_pci_find_root_bridge() uses the name (sic!) of the given
           device object to extract the segment and bus numbers of the PCI
           root bridge and passes them to acpi_get_pci_rootbridge_handle().
      
        8. acpi_get_pci_rootbridge_handle() browses the list of ACPI PCI
           root bridges and finds the one that matches the given segment
           and bus numbers.  Its handle is then used to initialize the
           ACPI handle of the PCI root bridge's device object by
           acpi_bind_one().  However, this is *exactly* the ACPI handle we
           started with in step 1.
      
      Needless to say, this is quite embarassing, but it may be avoided
      thanks to commit f3fd0c8a (ACPI: Allow ACPI handles of devices to be
      initialized in advance), which makes it possible to initialize the
      ACPI handle of a device before passing it to device_register().
      
      Accordingly, add a new __weak routine, pcibios_root_bridge_prepare(),
      defaulting to an empty implementation that can be replaced by the
      interested architecutres (x86 and ia64 at the moment) with functions
      that will set the root bridge's ACPI handle before its dev member is
      passed to device_register().  Make both x86 and ia64 provide such
      implementations of pcibios_root_bridge_prepare() and remove
      acpi_pci_find_root_bridge() and acpi_get_pci_rootbridge_handle() that
      aren't necessary any more.
      
      Included is a fix for breakage on systems with non-ACPI PCI host
      bridges from Bjorn Helgaas.
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      6c0cc950
  22. 03 1月, 2013 1 次提交
  23. 08 12月, 2012 1 次提交
  24. 06 12月, 2012 1 次提交
  25. 29 11月, 2012 2 次提交