- 22 12月, 2011 1 次提交
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由 Kay Sievers 提交于
The sysdev.h file should not be needed by any in-kernel code, so remove the .h file from these random files that seem to still want to include it. The sysdev code will be going away soon, so this include needs to be removed no matter what. Cc: Jiandong Zheng <jdzheng@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Wan ZongShun <mcuos.com@gmail.com> Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: "Venkatesh Pallipadi Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Matthew Garrett <mjg@redhat.com> Signed-off-by: NKay Sievers <kay.sievers@vrfy.org>
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- 04 10月, 2011 2 次提交
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由 Tomasz Stanislawski 提交于
This patch adds all the resources for TV drivers and devices for Samsung Exynos4 and S5PV210 platforms. Signed-off-by: NTomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> [m.szyprowski: squashed Exynos4 and S5PV210 patches and rewrote commit message] Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tomasz Stanislawski 提交于
This patch adds hdmiphy dedicated i2c controller definitions. Signed-off-by: NTomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> [m.szyprowski: renamed to i2c-hdmiphy and squashed Exynos4 and S5PV210 patches] Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 27 9月, 2011 1 次提交
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由 Sylwester Nawrocki 提交于
The sclk_cam clocks are now controlled by the top level FIMC media device driver bound to "s5p-fimc-md" platform device. Rename sclk_cam clocks so they accessible by the corresponding driver. Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 14 9月, 2011 1 次提交
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由 Boojin Kim 提交于
This patch makes Samsung S5PV210 to use DMA PL330 driver on DMADEVICE. The S5PV210 uses DMA generic APIs instead of SAMSUNG specific S3C-PL330 APIs. Signed-off-by: NBoojin Kim <boojin.kim@samsung.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NVinod Koul <vinod.koul@intel.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NVinod Koul <vinod.koul@intel.com>
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- 18 8月, 2011 1 次提交
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由 Vladimir Zapolskiy 提交于
This change replaces s3c-pl330.x clock device names with dma-pl330.x, otherwise there won't be a correspondence between clock device name and amba device name, thus clocks can't be enabled. Fixes runtime errors on clk_get() from drivers/dma/pl330.c: dma-pl330 dma-pl330.0: Cannot get operation clock. dma-pl330: probe of dma-pl330.0 failed with error -22 Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Acked-by: NBoojin Kim <boojin.kim@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 21 7月, 2011 2 次提交
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由 Kamil Debski 提交于
Add support for MFC device to plat-s5p, mach-exynos4, mach-s5pv210: - clock support - memory mapping and reserving - s5p_device_mfc platform device Signed-off-by: NKamil Debski <k.debski@samsung.com> Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Naveen Krishna Chatradhi 提交于
Move the duplicated code for SPDIF ops from S5PV210 and S5PC100. So, the same can be used in EXYNOS4. Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 20 7月, 2011 1 次提交
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由 Thomas Abraham 提交于
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 04 1月, 2011 1 次提交
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由 Kukjin Kim 提交于
This patch changes the clock registration code to use the s3c_register_clocks() followed by s3c_disable_clocks() instead of the loops it was using and cleanups the return of s3c24xx_register_clocks() because it includes it. Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 30 12月, 2010 1 次提交
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由 Thomas Abraham 提交于
This patch adds the SROM controller clock to the list of clocks to be enabled at boot time. It is required to be enabled at boot time since the modules connected over the SROM interface such as the Ethernet controller need an operational SROM. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 19 11月, 2010 1 次提交
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由 Jassi Brar 提交于
Add more information to I2S platform_devices in order to prepare them for new controller driver. Signed-off-by: NJassi Brar <jassi.brar@samsung.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 25 10月, 2010 8 次提交
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由 Seungwhan Youn 提交于
This patch adds DMA operation clock which is disabled as default. Signed-off-by: NSeungwhan Youn <sw.youn@samsung.com> Acked-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Seungwhan Youn 提交于
This patch adds warning about changing EPLL rate to notice that other driver that controls H/W, which is using EPLL, will has unknown effects by this EPLL rate change. Signed-off-by: NSeungwhan Youn <sw.youn@samsung.com> Acked-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Seungwhan Youn 提交于
This patch adds EPLL specific clock get_rate/set_rate operations on S5PV210. Signed-off-by: NSeungwhan Youn <sw.youn@samsung.com> Acked-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Seungwhan Youn 提交于
This patch fix wrong EPLL getting on setup clocks on S5PV210. Signed-off-by: NSeungwhan Youn <sw.youn@samsung.com> Acked-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Seungwhan Youn 提交于
This patch adds audio clocks(SCLK_AUDIO{0,1,2} and SCLK_AUDIO) to be initial as a sysclk on boot-time. Signed-off-by: NSeungwhan Youn <sw.youn@samsung.com> Acked-by: NJassi Brar <jassi.brar@samsung.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Seungwhan Youn 提交于
This patch add SCLK_SPDIF clock to support source clock of S/PDIF on S5PV210. Signed-off-by: NSeungwhan Youn <sw.youn@samsung.com> Acked-by: NJassi Brar <jassi.brar@samsung.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jaecheol Lee 提交于
This patch adds MOUT_DMC0 and SCLK_DMC0 for checking the dmc0 clock in CPUFREQ driver. Signed-off-by: NJaecheol Lee <jc.lee@samsung.com> Signed-off-by: NSangbeom Kim <sbkim73@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jaecheol Lee 提交于
Current fout_apll has fixed rate value. So CPUFREQ driver gets incorrect value when finding current CPU frequency. Because some operation level need to change APLL. Added get_rate function for fout_apll can give correct frequency value when calling get_rate function. Signed-off-by: NJaecheol Lee <jc.lee@samsung.com> Signed-off-by: NSangbeom Kim <sbkim73@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 08 10月, 2010 1 次提交
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由 Kukjin Kim 提交于
This patch removes following unused codes for removing build warnings. arch/arm/plat-samsung/adc.c:438: warning: unused variable 'flags' arch/arm/mach-s5pv210/clock.c:176: warning: 's5pv210_clk_ip4_ctrl' defined but not used Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 14 9月, 2010 2 次提交
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由 Marek Szyprowski 提交于
These clocks enables FIMC driver to operate on machines, which bootloader power gated FIMC devices to save power on boot. Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 MyungJoo Ham 提交于
CLK_GATE_IP3[8] is RESERVED. The port "I2C_HDMI_DDC" of CLK_GATE_IP3[10] is used as another I2C port. Therefore, defined the unused I2C-1 as another I2C there was left undefined but used. Signed-off-by: NMyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 05 7月, 2010 1 次提交
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由 MyungJoo Ham 提交于
1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were defined incorrectly. 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc, sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their twins defined in struct clk init_clocks_disable[] and struct clk init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK register to avoid the duplicated clock problem described below. NOTE: Duplicated Clock Problem Please note that each clock definition should access different control register; otherwise, the system may suffer lockups. For example, if we have two clock definitions "a" and "b" which access the same register (and the shift value). Then, when we do: module A clk = clk_get("a"); clk->clk_enable(clk); module B (context switch) clk = clk_get("b"); clk->clk_enable(clk); do something with clk. clk->clk_disable(clk); module A (context switch) do something with clk * At this point, the system may hang. Therefore, there should be no clock definitions with the same contol register/shift. If we need to create "aliases", then, creating child clocks sharing the clock should be fine. 3. Corrected other sclk_* shift values and access registers. Signed-off-by: NMyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title and message fix] Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 17 5月, 2010 16 次提交
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由 Thomas Abraham 提交于
Add sclk clocks of type 'struct clksrc_clk' clock. The 'group2' of clock clock sources is also added. This patch also changes the the 'id' member value of the uclk1 clock for instance instance 0 since there are 4 instances of the uclk1 clock. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
Add the sclk_audio(0/1/2) clocks and sclk_spdif clock of type 'struct clksrc_clk' clock. Also, add clk_pcmcdclk(0/1/2) clocks of type 'struct clk' clock. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
Add sclk_dac, sclk_mixer and sclk_hdmi clocks. These clocks are of type 'struct clksrc_clk' and so have a corresponding clock list. These clocks are also added to the list of clocks to be registered at boot time. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
This patch adds the following system clocks. 1. clk_sclk_hdmiphy 2. clk_sclk_usbphy0 3. clk_sclk_usbphy1 4. sclk_dmc (dram memory controller clock) 5. sclk_onenand Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
This patch adds the following. 1. Adds 'clk_sclk_hdmi27m' clock to represent the HDMI 27MHz clock. 2. Adds 'clk_vpllsrc; clock of type clksrc_clk to represent the input clock for VPLL. 3. Adds 'clk_sclk_vpll' clock of type clksrc_clk to represent the output of the MUX_VPLL mux. 4. Add clk_sclk_hdmi27m, clk_vpllsrc and clk_sclk_vpll to the list of clocks to be registered. 5. Adds boot time print of 'clk_sclk_vpll' clock rate. 6. Adds 'clk_fout_vpll' clock to plat-s5p such that it is reusable on other s5p platforms. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The clk_p83 clock, which is the PCLK clock for PSYS domain, is of type 'struct clk' whereas on S5PV210, this clock is suitable to be of type clksrc_clk clock (since it has a clock divider). So this patch replaces the 'struct clk' type clock to 'struct clksrc_clk' type clock for the PCLK PSYS clock. This patch modifies the following. 1. Removes definitions and usage of 'clk_p66' clock. 2. Adds 'clk_pclk_psys' clock which is of type 'struct clksrc_clk'. 3. Replaces all usage of clk_p66 with clk_pclk_psys clock. 4. Adds clk_pclk_psys into list of clocks to be registered. 5. Removes the sys_clks array since it is no longer required. Also the registration of clocks in sys_clks is also removed. 6. Remove the 'GET_DIV' as it is no longer required. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The clk_p83 clock, which is the PCLK clock for DSYS domain, is of type 'struct clk' whereas on S5PV210, this clock is suitable to be of type clksrc_clk clock (since it has a clock divider). So this patch replaces the 'struct clk' type clock to 'struct clksrc_clk' type clock for the PCLK DSYS clock. This patch modifies the following. 1. Remove definitions and usage of 'clk_p83' clock. 2. Adds 'clk_pclk_dsys' clock which is of type 'struct clksrc_clk'. 3. Replace all usage of clk_p83 with clk_pclk_dsys clock. 4. Adds clk_pclk_dsys into list of clocks to be registered. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The clk_h100 clock represents the IMEM clock for the MSYS domain. This clock rate of this clock is always half of the hclk_msys clock. There is an issue when getting the clock rate of the clk_h100 clock (clock get_rate hclk_h100 always returns clock rate that is equal to the hclk_msys clock rate). This patch modifies the following. 1. Moves the definition of the clk_h100 clock into the 'init_clocks' list with the appropriate parent, ctrlbit, enable and ops fields. 2. The name of the clock is changed from 'clk_h100' to 'hclk_imem' to represent more clearly that is represents the IMEM clock in the MSYS domain. 3. The function to get the clock rate of the hclk_imem clock is added. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The clk_p100 clock, which is the PCLK clock for MSYS domain, is of type 'struct clk' whereas on S5PV210, this clock is suitable to be of type clksrc_clk clock (since it has a choice of clock source and a pre-divider). So this patch replaces the 'struct clk' type clock to 'struct clksrc_clk' type clock for the PCLK MSYS clock. This patch modifies the following. 1. Remove definitions and usage of 'clk_p100' clock. 2. Adds 'clk_pclk_msys' clock which is of type 'struct clksrc_clk'. 3. Replace all usage of clk_p100 with clk_pclk_msys clock. 4. Adds clk_pclk_msys into list of clocks to be registered. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The clk_h133 clock, which is the HCLK clock for PSYS domain, is of type 'struct clk' whereas on S5PV210, this clock is suitable to be of type clksrc_clk clock (since it has a choice of clock source and a pre-divider). So this patch replaces the 'struct clk' type clock to 'struct clksrc_clk' type clock for the HCLK PSYS clock. This patch modifies the following. 1. Remove definitions and usage of 'clk_h133' clock. 2. Adds 'clk_hclk_psys' clock which is of type 'struct clksrc_clk'. 3. Replace all usage of clk_h133 with clk_hclk_psys clock. 4. Adds clk_hclk_psys into list of clocks to be registered. 5. Removes the clock rate calculation of hclk133 and replaces it with code that derives the HCLK PSYS clock rate from the clk_hclk_psys clock. 6. Modify printing of the system clock rates. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The clk_h166 clock, which is the HCLK clock for DSYS domain, is of type 'struct clk' whereas on S5PV210, this clock is suitable to be of type clksrc_clk clock (since it has a choice of clock source and a pre-divider). So this patch replaces the 'struct clk' type clock to 'struct clksrc_clk' type clock for the HCLK DSYS clock. This patch modifies the following. 1. Remove definitions and usage of 'clk_h166' clock. 2. Adds 'clk_sclk_a2m' clock which is one of possible parent clock sources for the DSYS HCLK clock. 3. Adds 'clk_hclk_dsys' clock which is of type 'struct clksrc_clk'. 4. Replace all usage of clk_h166 with clk_hclk_dsys clock. 5. Adds clk_sclk_a2m and clk_hclk_dsys into list of clocks to be registered. 6. Removes the clock rate calculation of hclk166 and replaces it with code that derives the HCLK DSYS clock rate from the clk_hclk_dsys clock. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The clk_h200 represents the HCLK for the MSYS domain. This clock is of type 'struct clk' but on V210, it is more suitable to be of type 'struct clksrc_clk' (since it is a divided version of the armclk). The replacement clock is renamed as clk_hclk_msys to indicate that it represents the HCLK for MSYS domain. This patch modifies the following. 1. Removes the usage of the clk_h200 clock. 2. Adds the new clock 'clk_hclk_msys'. 3. Adds clk_hclk_msys to the list of sysclks to be registered. 4. Modifies the hclk_msys clock rate calculation procedure to be based on the new clk_hclk_msys clock. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
This patch modifies the following. 1. Adds arm clock 'clk_armclk' of type clksrc_clk clock type. 2. Adds arm clock to the list of system clocks 'sysclks' for registering it along with other system clocks. 3. Modifies the armclk clock rate calculation procedure to be based on the new clk_armclk clock. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The assignment of clock rates for fout apll/mpll/epll is moved further up in the s5pv210_setup_clocks function because the subsequent patches require the clock rate of fout clocks to be setup. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
This patch modifies the following. 1. Registers the mout_apll clksrc_clk clock. 2. The mout_mpll and mout_epll clocks were registered as 'struct clk' types and then their parents were setup using the s3c_set_clksrc function. This patch reduces the two steps into one by registering the mout_mpll and mout_epll clocks using the s3c_register_clksrc function. 3. As per point 2 above, the init_parents array is no longer required. So the mout clocks are now put together in a new array named 'sysclks'. The sysclks array will list the system level clocks and more clocks will be added to it in the subsequent patches. 4. The clks array is left empty because of the movement of mpll and epll clocks into the sysclks array. It is not deleted since subsequent patches will add clocks into this array. Signed-off-by: Thomas Abraham <thomas.ab <at> samsung.com> Signed-off-by: Kukjin Kim <kgene.kim <at> samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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由 Thomas Abraham 提交于
The system clock definitions are currently defined below the peripheral clock definitions in the V210 clock code. For the V210 clock updates that follow this patch, it is required that the system clock definitions such as the mout_apll and mout_mpll be defined prior to the device clock definitions. This patch re-arranges the system clock defintions for the clock updates that follow this patch. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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