1. 16 7月, 2008 8 次提交
  2. 16 6月, 2008 2 次提交
  3. 06 6月, 2008 1 次提交
  4. 29 4月, 2008 8 次提交
  5. 12 3月, 2008 1 次提交
  6. 29 1月, 2008 17 次提交
  7. 22 1月, 2008 1 次提交
    • D
      [MIPS] Malta: Fix reading the PCI clock frequency on big-endian · 0487de91
      Dmitri Vorobiev 提交于
      The JMPRS register on Malta boards keeps a 32-bit CPU-endian
      value. The readw() function assumes that the value it reads is a
      little-endian 16-bit number. Therefore, using readw() to obtain
      the value of the JMPRS register is a mistake. This error leads
      to incorrect reading of the PCI clock frequency on big-endian
      during board start-up.
      
      Change readw() to __raw_readl().
      
      This was tested by injecting a call to printk() and verifying
      that the value of the jmpr variable was consistent with current
      setting of the JP4 "PCI CLK" jumper.
      Signed-off-by: NDmitri Vorobiev <dmitri.vorobiev@gmail.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      0487de91
  8. 12 1月, 2008 2 次提交
    • A
      [MIPS] Replace 40c7869b kludge · e452e94e
      Atsushi Nemoto 提交于
      Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e452e94e
    • D
      [MIPS] Malta: Fix software reset on big endian · 84c21e25
      Dmitri Vorobiev 提交于
      I noticed that the commit f1974653
      (MIPS Tech: Get rid of volatile in core code) broke the software
      reset functionality for MIPS Malta boards in big-endian mode.
      
      According to the MIPS Malta board user's manual, writing the magic
      32-bit GORESET value into the SOFTRES register initiates board soft
      reset. My experimentation has shown that the endianness of the GORESET
      integer should thereby be the same as the endianness, which has been
      set for the CPU itself. The writew() function used to write the magic
      value in the code introduced by the commit mentioned above, however,
      swaps bytes for big-endian kernels and transfers 16 bits instead of 32.
      
      The patch below replaces the writew() function by the __raw_writel()
      routine, which leaves the byte order intact and transfers the whole
      MIPS machine word. Trivial code cleanup (replacing spaces by a tab
      and cutting oversized lines to make checkpatch.pl happy) is also
      included.
      
      The patch was tested using a Malta evaluation board running in both
      BE and LE modes. For both modes, software reset was fully functional
      after the change.
      
      P.S. I suspect that the same commit broke the "standby" functionality
      for MIPS Atlas boards. However, I did not touch the Atlas code as I
      don't have such board at my disposal and also because the linux-mips.org
      Web site claims that Atlas support is scheduled for removal.
      Signed-off-by: NDmitri Vorobiev <dmitri.vorobiev@gmail.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      84c21e25