The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A31 SoC has a GMAC gigabit ethernet controller supporting
MII, GMII, RGMII modes. Add pin muxing options for these modes.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The pinctrl device is also an interrupt controller for external
interrupts. Add the missing #interrupt-cells property.

Also remove the unused #address-cells property.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
[hdegoede@redhat.com: make the same change for sun4i, sun5i and sun6i]
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The unit-address doesn't match the reg property. Since the reg property is
correct, change the unit-address accordingly.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

That will allow to use the CPU_METHOD_OF_DECLARE definition we did previously.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A31 SoC has a different pin controller for PL and PM banks.
Define this new controller in the device tree.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>

The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>

Add nodes for the 4 mmc controllers found on A31 SoCs to
arch/arm/boot/dts/sun6i-a31.dtsi.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add clk-nodes for the mmc clocks.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This adds  pin-muxing info for the mmc controller / port combinations which
are known to be used on actual boards.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Enable the performance monitoring unit found in the A31 SoCs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>

Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the
controller and the devices supported that can use DMA.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The DT are supposed to be ordered by physical address. Move the NMI node where
it belongs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The Allwinner A31 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The prcm lives at address 0x01f01400 as the reg entry in its node already
correctly indicates, rename the node to match this.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The IRQ line used in sun6i-a31.dtsi for the NMI controller is wrong.
This causes a IRQ storm since the NMI controller is repeatedly fired.
This patch fixes this problem assigning the correct IRQ number to the
NMI controller.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NCarlo Caione <carlo@caione.org>
Cc: maxime.ripard@free-electrons.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1395939759-11135-2-git-send-email-carlo@caione.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: NCarlo Caione <carlo@caione.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Acked-by: maxime.ripard@free-electrons.com
Link: http://lkml.kernel.org/r/1395256879-8475-3-git-send-email-carlo@caione.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The watchdog compatibles were following a different pattern than the one found
in the other devices. Now that the driver supports the right pattern, switch to
it in the DT.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Switch the device tree to the new compatibles introduced in the timer driver
to have a common pattern accross all Allwinner SoCs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The i2c controllers have a few muxing options on the A31. Enable the
ones found in the A31 Colombus board.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A31 has 4 I2C controllers that are the same than the one in the
other Allwinner SoCs, except for the fact that they are asserted in
reset by the reset unit.

Add these i2c controllers to the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The module 0 clock compatibles were changed between the time the patch was sent
and it was merged. Update the compatibles.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Switch the device tree to the new compatibles introduced in the clock drivers
to have a common pattern accross all Allwinner SoCs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some UART aliases have been defined, but not all of them. Add the remaining
ones to be consistent and to ease the parsing of the DT by the bootloaders.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A31 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A31 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org # 3.12+
Signed-off-by: NOlof Johansson <olof@lixom.net>

The A31 has a reset controller IP that maintains a few other IPs in
reset, among which we can find the UARTs, high speed timers or the I2C.
Now that we have support for them, add the reset controllers to the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The APB2 clocks gates are only a 32 bits register wide, and not 2 as set
currently in the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that the clock driver has support for the A31 clocks, we can add
them to the DTSI and start using them in the relevant hardware blocks.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A31 has a different set of pins than the one found on the A10 and
A13. Now that we have support for the A31 pin set in the pinctrl driver,
we can enable it in the DTSI with its own compatible.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a
PowerVR GPU.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>