1. 14 7月, 2011 1 次提交
  2. 11 4月, 2011 1 次提交
  3. 07 4月, 2011 1 次提交
  4. 15 3月, 2011 1 次提交
  5. 01 2月, 2011 1 次提交
  6. 28 1月, 2011 1 次提交
  7. 27 1月, 2011 1 次提交
  8. 29 11月, 2010 1 次提交
  9. 21 10月, 2010 2 次提交
  10. 12 10月, 2010 1 次提交
  11. 20 7月, 2010 1 次提交
  12. 05 7月, 2010 1 次提交
  13. 18 5月, 2010 1 次提交
  14. 07 5月, 2010 1 次提交
  15. 08 4月, 2010 1 次提交
  16. 17 2月, 2010 1 次提交
  17. 18 1月, 2010 1 次提交
    • M
      bnx2: Save statistics during reset. · 354fcd77
      Michael Chan 提交于
      MTU changes, ring size changes, etc cause the chip to be reset and the
      statisctics flushed.  To keep track of the accumulated statistics, we
      add code to save the whole statistics block before reset.  We also
      modify the macros and statistics functions to return the sum of the
      saved and current counters.
      
      Based on original patch by Breno Leitao <leitao@linux.vnet.ibm.com>
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      354fcd77
  18. 04 12月, 2009 1 次提交
  19. 03 12月, 2009 1 次提交
  20. 28 10月, 2009 1 次提交
  21. 23 8月, 2009 2 次提交
  22. 16 8月, 2009 1 次提交
  23. 09 6月, 2009 1 次提交
  24. 18 5月, 2009 1 次提交
    • E
      bnx2: bnx2_tx_int() optimizations · d62fda08
      Eric Dumazet 提交于
      When using bnx2 in a high transmit load, bnx2_tx_int() cost is pretty high.
      
      There are two reasons.
      
      One is an expensive call to bnx2_get_hw_tx_cons(bnapi) for each freed skb
      
      One is cpu stalls when accessing skb_is_gso(skb) / skb_shinfo(skb)->nr_frags
      because of two cache line misses.
      (One to get skb->end/head to compute skb_shinfo(skb),
       one to get is_gso/nr_frags)
      
      This patch :
      
      1) avoids calling bnx2_get_hw_tx_cons(bnapi) too many times.
      
      2) makes bnx2_start_xmit() cache is_gso & nr_frags into sw_tx_bd descriptor.
         This uses a litle bit more ram (256 longs per device on x86), but helps a lot.
      
      3) uses a prefetch(&skb->end) to speedup dev_kfree_skb(), bringing
        cache line that will be needed in skb_release_data()
      
      result is 5 % bandwidth increase in benchmarks, involving UDP or TCP receive
       & transmits, when a cpu is dedicated to ksoftirqd for bnx2.
      
      bnx2_tx_int going from 3.33 % cpu to 0.5 % cpu in oprofile
      
      Note : skb_dma_unmap() still very expensive but this is for another patch,
      not related to bnx2 (2.9 % of cpu, while it does nothing on x86_32)
      Signed-off-by: NEric Dumazet <dada1@cosmosbay.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d62fda08
  25. 05 4月, 2009 1 次提交
    • M
      bnx2: Use request_firmware() · 57579f76
      Michael Chan 提交于
      Based on original patch by Ben Hutchings <ben@decadent.org.uk> and
      Bastian Blank <waldi@debian.org>, with the following main changes:
      
      Separated the mips firmware and rv2p firmware into different files
      to make it easier to update them separately.
      
      Added some code to fixup the rv2p code with run-time information
      such as PAGE_SIZE.
      
      Update version to 2.0.0.
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      57579f76
  26. 13 2月, 2009 1 次提交
  27. 17 12月, 2008 2 次提交
  28. 03 12月, 2008 1 次提交
    • M
      bnx2: Add workaround to handle missed MSI. · efba0180
      Michael Chan 提交于
      The bnx2 chips do not support per MSI vector masking.  On 5706/5708, new MSI
      address/data are stored only when the MSI enable bit is toggled.  As a result,
      SMP affinity no longer works in the latest kernel.  A more serious problem is
      that the driver will no longer receive interrupts when the MSI receiving CPU
      goes offline.
      
      The workaround in this patch only addresses the problem of CPU going offline.
      When that happens, the driver's timer function will detect that it is making
      no forward progress on pending interrupt events and will recover from it.
      
      Eric Dumazet reported the problem.
      
      We also found that if an interrupt is internally asserted while MSI and INTA
      are disabled, the chip will end up in the same state after MSI is re-enabled.
      The same workaround is needed for this problem. 
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Tested-by: NEric Dumazet <dada1@cosmosbay.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      efba0180
  29. 29 11月, 2008 1 次提交
  30. 13 11月, 2008 2 次提交
  31. 10 10月, 2008 1 次提交
  32. 19 9月, 2008 3 次提交
  33. 19 7月, 2008 1 次提交
  34. 15 7月, 2008 1 次提交