[How&Why]
add params to send FEC status to firmware
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Pipe input DSC bpc has a type mismatch with maximum DSC
input bpc - align the maximum with the pipe input type,
unsigned integer.

When checking the type we shoudl also check for an
implicit value of 0 and align with what the spreadsheet
does - default to max.

Rename output_bpc to dsc_input_bpc to reflect what the
field is actually used for.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
When on the desktop freesync is not enabled,
doing a frame stretch causes the TV to display
undesired output.

[HOW]
By changing the logic so that when ever fresync
is supported the TV is notified we are in fressync
instead on a non fresync state.
Signed-off-by: NHarry VanZyllDeJong <hvanzyll@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
The driver always wants to synchronize streams
to the first edge of master's vsync pulse.
In order to determine that we can read timing
flags that are used to program vsync.

Master stream's vsync polarity - Multi Display Stream Synchronization edge:

        Negative               -              Falling Edge

        Positive               -              Rising Edge
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Need to be able to trigger software hotplug for MST connectors

[How]
For unplug the driver calls to disable topologies manager
that connector is attached to. For plugging in it does the
whole rediscovery of all connectors in drm device and enbles their
topologies if attached.

The interface for MST connectors works in the following way:

1. To disconnect all MST topologies currently connected:
   echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst

2. To reconnect/rediscover all topologies that are physically
connected to the card:
   echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst

A related fix which has been merged with this patch
Leo Ma(Hanghong Ma)'s work:

Set power states before disable MST topology
[Why]
	When we try to disable MST topology from the
	debugfs entry, some receiver will hang.
[How]
	Set DPCD 600h power states to
	2(power down mode)before disable MST topology.
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why/how]
Skip logic that sets preffered link settings
and just retrain with new link_settings from Debugfs
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DCN3 is not reusing DCN1 mask_sh_list, causing
SURFACE_FLIP_INT_MASK missing in the mapping.

[How]
Add the corresponding entry to DCN3 list.
Signed-off-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Commit 1c85f3db
("drm/amd/display: Add kernel doc to crc_rd_wrk
field") adds kernel doc for crc_rd_wrk field in
amdgpu_dm.h but it's incorrectly formatted.
Make htmldocs warns:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:398: warning:
Incorrect use of kernel-doc format:          * @crc_rd_wrk

[How]
Tweak the kernel doc for crc_rd_wrk.

Fixes: 1c85f3db ("drm/amd/display: Add kernel doc to crc_rd_wrk field")
Signed-off-by: NWayne Lin <Wayne.Lin@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why/how]
Due to compiler optimization the values would be
passed to the division function uninitialized
causing a div by zero. Initialize the numerator
and denominator to 0 and 1 to prevent division
by zero.
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Currently to view the DCC_EN bit the entire DTN log
must be dumped. A compact method to view the DCC_EN
bit is desirable.

[how]
Introduce new debugfs interface that only dumps the
DCC_EN bit.

Example usage:
cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
Signed-off-by: NVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add debug flag for an option to disable min fclk.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add debug prints for SMU messages with regard to
versions, clocks, and more.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NRobin Singh <Robin.Singh@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We need to keep track of the number of eDP links to
properly enumerate edp panel control instance.

[How]
Added dc_edp_id_count to dc_context to keep track of
number of eDP links.
Signed-off-by: NJake Wang <haonan.wang2@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Functionality of LTTPR is reporter through the DPCD register

[How]
Expose a interface in debugfs to read the current status of
LTTPR as reported from the device's DPCD register
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]

The OTG_VUPDATE_KEEPOUT register and fields is
available on DCN10, and named the same in DCN20.

[How]

Move register definition and programming function
to dcn10 optc.

There is no functional change.
Signed-off-by: NLeo Li <sunpeng.li@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
There is case when the userspace like IGT test updates the custom
timings, i.e. the number of active lines CRTC property value,
and without committing the change, followed by
resetting the display, creating FB and plane to the pipe
and committing. The NULL pointer of pipe_ctx->plane_state
occurs and result in kernel crash. We need to avoid that.

[how]
add pointer check for the dc_plane_state of the pipe context in
the call of committing planes for stream in DC component.
Signed-off-by: NRobin Singh <robin.singh@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
     In MST setup, we'd use MST downstream AUX to
     dump the DPRX CRCs from sink device.

[how]
     Assign the mst_port->aux to read DPCD registers.
Signed-off-by: NDavid (Dingchen) Zhang <dingchen.zhang@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Today a parameter is passed to dmub_srv_send_gpint_command
which specifies the max amount of time to wait for the command
to be acked.
This parameter instead specifies the number of times to check if
the command was acked.
We wish to add a lower bound to the timeout, which can be
accomplished by using a delay or a timestamp.
It has been decided to use udelay instead of a timestamp simply
because we don't want to expose a high precision counter if it
doesn't yield large benefits.

[How]
Add udelay(1) between each for loop iteration.
Signed-off-by: NWyatt Wood <wyatt.wood@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
GPINT command to get PSR state from FW times out.

[How]
Add retry to get valid PSR state.
Signed-off-by: NWyatt Wood <wyatt.wood@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

struct mod_hdcp is declared twice. One is declared at 33rd line.
The blew one is not needed. Remove the duplicate.
Signed-off-by: NWan Jiabing <wanjiabing@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use uintptr_t rather than uint64_t.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>

[why]
Our CI enables drm.debug=0x4 logs and the dmesg is flooded with cursor
updates. We probably want to avoid spamming the log with DRM_DEBUG_KMS.

[how]
Define and use pr_debug macros instead of a few spammy DRM_DEBUG_*'s.
Signed-off-by: NVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Otherwise, below errors will be found on DIMGREY_CAVEFISH with DCN302.

Error log observed in driver load:
[drm:amdgpu_dm_irq_register_interrupt [amdgpu]] *ERROR* DM_IRQ: invalid irq_source: 0!

Error observed in mode1_rest sequence:
[   27.265920] #PF: supervisor read access in kernel mode
[   27.265941] #PF: error_code(0x0000) - not-present page
[   27.265956] PGD 0 P4D 0
[   27.265967] Oops: 0000 [#1] SMP NOPTI
[   27.265979] CPU: 0 PID: 1360 Comm: cat Tainted: G        W         5.11.0-99b3786c1770 #20210323
[   27.266005] Hardware name: System manufacturer System Product Name/PRIME Z390-A, BIOS 1401 11/26/2019
[   27.266033] RIP: 0010:dal_irq_service_ack+0x25/0x60 [amdgpu]
[   27.266203] Code: 5d 5d c3 66 90 0f 1f 44 00 00 55 83 fe 61 48 89 e5 77 27 89 f0 48 8d 04 40 48 c1 e0 04 48 03 47 08 74 17 48 8b 50 28 48 89 c6 <48> 8b 52 08 48 85 d2 74 20 e8 1d 64 45 c9 5d c3 89 f2 48 c7 c7 f0
[   27.266248] RSP: 0018:ffffa115824a3c08 EFLAGS: 00010082
[   27.266270] RAX: ffffffffc0942c10 RBX: ffffffffc0942c10 RCX: 0000000000000000
[   27.266288] RDX: 0000000000000000 RSI: ffffffffc0942c10 RDI: ffff88d509cba7a0
[   27.266312] RBP: ffffa115824a3c08 R08: 0000000000000000 R09: 0000000000000001
[   27.266335] R10: ffffa115824a3b20 R11: ffffa115824a3b58 R12: ffff88d509cba7a0
[   27.266353] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000246
[   27.266377] FS:  00007fb3e2438580(0000) GS:ffff88d50dc00000(0000) knlGS:0000000000000000
[   27.266402] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   27.266417] CR2: 0000000000000008 CR3: 000000083e5ac006 CR4: 00000000003706f0
[   27.266441] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[   27.266464] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[   27.266483] Call Trace:
[   27.266491]  dal_irq_service_set+0x31/0x80 [amdgpu]
[   27.266639]  dc_interrupt_set+0x24/0x30 [amdgpu]
[   27.266775]  amdgpu_dm_set_dmub_trace_irq_state+0x22/0x30 [amdgpu]
[   27.266920]  amdgpu_irq_update+0x57/0xa0 [amdgpu]
[   27.267030]  amdgpu_irq_gpu_reset_resume_helper+0x64/0xa0 [amdgpu]
[   27.267135]  amdgpu_do_asic_reset+0x211/0x420 [amdgpu]
[   27.267232]  amdgpu_device_gpu_recover+0x517/0xa70 [amdgpu]
[   27.267325]  gpu_recover_get+0x2e/0x60 [amdgpu]
[   27.267421]  simple_attr_read+0x6b/0x130
[   27.267441]  debugfs_attr_read+0x49/0x70
[   27.267454]  full_proxy_read+0x5c/0x90
[   27.267474]  vfs_read+0xa1/0x190
[   27.267486]  ksys_read+0xa7/0xe0
[   27.267501]  __x64_sys_read+0x1a/0x20
[   27.267521]  do_syscall_64+0x37/0x80
[   27.267541]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[   27.267562] RIP: 0033:0x7fb3e2356142
Signed-off-by: NGuchun Chen <guchun.chen@amd.com>
Reviewed-by: NLeo (Hanghong) Ma <hanghong.ma@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDiego Viola <diego.viola@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

When encoder validation of a display mode fails, retry with less bandwidth
heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
to support 4k60Hz output, which previously failed silently.

On some setups, while the monitor and the gpu support display modes with
pixel clocks of up to 600MHz, the link encoder might not. This prevents
YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be
possible. However, which color mode is used is decided before the link
encoder capabilities are checked. This patch fixes the problem by retrying
to find a display mode with YCbCr420 enforced and using it, if it is
valid.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NWerner Sembach <wse@tuxedocomputers.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following features/fixes:
- LTTPR improvements
- Disable MALL when SMU not present
- Fix bug in HW that causes P-State to hang when DPG is enabled in
  certain conditions
- Update code path for enabling DPG
- Update display endpoint control path
- Add dynamic link encoder selection
- Fix debugfs MST topology to dump from the root MST node
- Enable DP DSC Compliance automation for Linux
- ASSR is enabled only when DPCD is supported and the display
  connected is internal
- Added kernel trace event to print real-time refresh rate value
  to debug VRR issues
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Bring-up purpose code to disable DMUB calling into
SMU and timeout for MALL when SMU is not present.

[How]
Disable MALL when SMU is not present.
Signed-off-by: NChris Park <Chris.Park@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add log for easier debug purposes.
Signed-off-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
There is a bug in HW that causes P-State to hang when DPG is enabled in
certain conditions.

[HOW]
The solution is to force MIN_TTU_VBLANK register to maximum value
whenever DPG has been enabled.
Make stream do a full update on test pattern change, so that the TTUs
get updated.
When DPG is enabled, update the ttu_regs.min_ttu_vblank field of each
pipe in the stream's topology to the maximum value (0xffffff).

v2: squash in build fix for when DCN is not defined (Alex)
Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
We want to make enabling test pattern a part of the
stream update code path. This change is the first step
towards that goal.
Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some display endpoints may be dynamically mapped to the link encoders
which drive them.

[How]
Update the code paths for display enabling/disabling to accommodate
the dynamic association between links and link encoders.
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some display endpoints may be programmably mapped to compatible link
encoders. The assignment of link encoders to links has to be dynamic to
accommodate the increased flexibility in comparison to conventional
display endpoints.

[How]
- Add link encoder assignment tracking variables.
- Execute link encoder assignment algorithm before enabling link and
release link encoders from links once they are disabled.
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
The drm dump_topology function was previously called on all
DP connectors. This resulted in empty topology dumps for those
connectors which weren't root MST nodes.

[how]
Make sure we only dump topology from the root MST node.
Signed-off-by: NEryk Brol <eryk.brol@amd.com>
Reviewed-by: NAurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Some systems can enable LTTPR through bits in BIOS, while other systems
can be configured at boot to enable LTTPR. Some configs enable
Non-Transparent mode, while others enable Transparent mode.
Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
There are three possible modes for LTTPR:
- Non-LTTPR mode, where AUX timeout is 400 us and no per-hop link
training is done
- LTTPR Transparent mode, where AUX timeout is 3200 us and no per-hop
link training is done
- LTTPR Non-Transparent mode, where AUX timeout is 3200 us and per-hop
link training is done

[HOW]
Use an enum instead of a bool to track LTTPR state; modify comparisons
accordingly.
Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
The logic to toggle LTTPR transparent/non-transparent requires 2 flags
provided by BIOS

[HOW]
Repurpose the interface to get dce caps so both LTTPR querying functions
can use them.
Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Renaming structure to better indicate its meaning.
Signed-off-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Acked-by: NAnthony Koo <Anthony.Koo@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Word "remainder" was misspelled as "reminder" in
reduceSizeAndFraction method variable.

[how]
Fix the spelling.
Signed-off-by: NVladimir Stempen <vladimir.stempen@amd.com>
Reviewed-by: NAlexander Deucher <alexander.deucher@amd.com>
Reviewed-by: NBindu R <Bindu.R@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Reviewed-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>