Skip to content

K
Kernel

openeuler / Kernel
接近 2 年 前同步成功

通知 8
Star 0
Fork 0
K
Kernel
切换分支/标签
  1. 08 3月, 2011 1 次提交
  3. 22 12月, 2010 1 次提交
  5. 25 2月, 2010 5 次提交
    • P
      OMAP3/4 clock: split into per-chip family files · 657ebfad
      由 Paul Walmsley 提交于 
      clock34xx_data.c now contains data for the OMAP34xx family, the
OMAP36xx family, and the OMAP3517 family, so rename it to
clock3xxx_data.c.  Rename clock34xx.c to clock3xxx.c, and move the
chip family-specific clock functions to clock34xx.c, clock36xx.c, or
clock3517.c, as appropriate.  So now "clock3xxx.*" refers to the OMAP3
superset.

The main goal here is to prepare to compile chip family-specific clock
functions only for kernel builds that target that chip family.  To get to
that point, we also need to add CONFIG_SOC_* options for those other
chip families; that will be done in future patches, planned for 2.6.35.

OMAP4 is also affected by this.  It duplicated the OMAP3 non-CORE DPLL
clkops structure.  The OMAP4 variant of this clkops structure has been
removed, and since there was nothing else currently in clock44xx.c, it
too has been removed -- it can always be added back later when there
is some content for it.  (The OMAP4 clock autogeneration scripts have been
updated accordingly.)
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ranjith Lohithakshan <ranjithl@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
      657ebfad
    • M
      OMAP3630: Clock: Workaround for DPLL HS divider limitation · a7e069fc
      由 Mike Turquette 提交于 
      This patch implements a workaround for the DPLL HS divider limitation
in OMAP3630 as given by Errata ID: i556.

Errata:
When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx).
The reset value gets loaded instead of the previous value.
The following HSDIVIDERs exhibit above behavior:
. DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits)
. DPLL3 : M3 (CM_CLKEN_PLL[12] register bit).

Work Around:
It is mandatory to apply the following sequence to ensure the write
value will
be loaded in DPLL HSDIVIDER FSM:
The global sequence when using PWRDN bit is the following:
. Disable Mx HSDIVIDER clock output related functional clock enable bits
        (in CM_FCLKEN_xxx / CM_ICLKEN_xxx)
. Enable PWRDN bit of HSDIVIDER
. Disable PWRDN bit of HSDIVIDER
. Read current HSDIVIDER register value
. Write different value in HSDIVIDER register
. Write expected value in HSDIVIDER register
. Enable Mx HSDIVIDER clock output related functional clocks
        (CM_FCLKEN_xxx / CM_ICLKEN_xxx)
Signed-off-by: NMike Turquette <mturquette@ti.com>
Signed-off-by: NVishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: NVijaykumar GN <vijaykumar.gn@ti.com>
[paul@pwsan.com: updated patch to apply; made workaround function static;
 marked as being 36xx-specific]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      a7e069fc
    • S
      OMAP3 clock: Check return values for clk_get() · a51ba284
      由 Sanjeev Premi 提交于 
      This patch checks if clk_get() returned success for
the clocks used in function omap2_clk_arch_init().

This version incorporates review comments from
Kevin Hilman and Paul Walmsley.
Signed-off-by: NSanjeev Premi <premi@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      a51ba284
    • R
      AM35xx: Add clock support for new modules on AM35xx · 3cc4a2fc
      由 Ranjith Lohithakshan 提交于 
      This patch adds clock support for the following AM35xx modules
	- Ethernet MAC
	- CAN Controller (HECC)
	- New MUSB OTG Controller with integrated Phy
	- Video Processing Front End (VPFE)
	- Additional UART (UART4)
Signed-off-by: NRanjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      3cc4a2fc
    • R
      OMAP2/3 clock: Extend find_idlest() to pass back idle state value · 419cc97d
      由 Ranjith Lohithakshan 提交于 
      Current implementation defines clock idle state indicators based on the
cpu information (cpu_is_omap24xx() or cpu_is_omap34xx()) in a system wide
manner. This patch extends the find_idlest() function in clkops to pass
back the idle state indicator for that clock, thus allowing idle state
indicators to be defined on a per clock basis if required.

This is specifically needed on AM35xx devices as the new IPSS clocks
indicates the idle status (0 is idle, 1 is ready) in a way just
opposite to how its handled in OMAP3 (0 is ready, 1 is idle).
Signed-off-by: NRanjith Lohithakshan <ranjithl@ti.com>
[paul@pwsan.com: updated to apply after commit 98c45457 et seq.]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      419cc97d
  7. 16 2月, 2010 1 次提交
  9. 30 1月, 2010 4 次提交
    • P
      OMAP2/3/4 clock: rename and clean the omap2_clk_init() functions · e80a9729
      由 Paul Walmsley 提交于 
      Rename the omap2_clk_init() in the OMAP2, 3, and 4 clock code to be
omap2xxx_clk_init(), omap3xxx_clk_init(), etc.  Remove all traces of
the (commented) old virt_prcm_set code from omap3xxx_clk_init() and
omap4xxx_clk_init(), since this will be handled with the OPP code that
is cooking in the PM branch.

After this patch, there should be very little else in the clock code
that blocks a multi-OMAP 2+3 kernel.  (OMAP2420+OMAP2430 still has some
outstanding issues that need to be resolved; this is pending on some
additions to the hwmod data.)
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      e80a9729
    • P
      OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only · feec1277
      由 Paul Walmsley 提交于 
      omap2_clk_prepare_for_reboot() is only applicable to OMAP2xxx chips,
so rename it to omap2xxx_clk_prepare_for_reboot() and only call it when
running on OMAP2xxx chips.  Remove the old stub in the OMAP3 clock code.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      feec1277
    • P
      OMAP2/3 clock: remove unnecessary includes and clean up header · da4d2904
      由 Paul Walmsley 提交于 
      Now that almost all of the code has been removed from clock2xxx.c and
clock34xx.c, many of the includes are now unnecessary and can be removed.
While we're here, standardize the initial comment blocks.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Jouni Högander <jouni.hogander@nokia.com>
      da4d2904
    • P
      OMAP2/3 clock: clean up omap*_clk_arch_init() · 4680c29f
      由 Paul Walmsley 提交于 
      In the OMAP3xxx clock code, remove the #ifdef CONFIG_ARCH_OMAP3 in
clock34xx.c, since this file is only compiled for OMAP3xxx builds.  Also,
rename omap2_clk_arch_init in this file to omap3xxx_clk_arch_init() to
pave the way for multi-OMAP kernels.  Ensure that it is not executed
on non-OMAP3xxx systems.

In the OMAP2xxx clock code, rename omap2_clk_arch_init in this file to
omap2xxx_clk_arch_init() to pave the way for multi-OMAP kernels.
Ensure that it is not executed on non-OMAP2xxx systems.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      4680c29f
  11. 29 1月, 2010 1 次提交
    • P
      OMAP3 clock: split out DPLL3 M2 divider functions into mach-omap2/clkt34xx_dpll3m2.c · 35e424e2
      由 Paul Walmsley 提交于 
      Split the DPLL3 M2 divider clock functions out of clock34xx.c and move
them into mach-omap2/clkt34xx_dpll3m2.c. This is intended to make the
clock code easier to understand, since all of the functions needed to
manage the OMAP3 DPLL3 M2 divider are now located in their own file,
rather than being mixed with other, unrelated functions.

Clock debugging is also now more finely-grained, since the DEBUG macro
can now be defined for the DPLL3 M2 clock alone.  This should reduce
unnecessary console noise when debugging DVFS.

Also, if at some future point the mach-omap2/ directory is split
into OMAP2/3/4 variants, this clkt file can be placed in the mach-omap34xx/
directory, rather than shared with other chip types that don't use this
clock type.

This patch also lays the groundwork to skip compilation of this
code on OMAP3 chips that don't support DVFS (e.g., AM35xx) via
the Makefile, rather than via #ifdefs.

Thanks to Alexander Shishkin <virtuoso@slind.org> for his comments to
improve the patch description.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Jouni Högander <jouni.hogander@nokia.com>
Cc: Alexander Shishkin <virtuoso@slind.org>
      35e424e2
  13. 27 1月, 2010 1 次提交
    • P
      OMAP2/3/4 clock: combine all omap2_clk_functions · 69ecefca
      由 Paul Walmsley 提交于 
      The struct clk_functions for OMAP2, 3, and 4 are all essentially the
same, so combine them.  This removes one multi-OMAP kernel impediment
and saves memory on multi-OMAP builds.

The stubs for omap2_clk_{init,exit}_cpufreq() code will removed once
the OPP layer code that's currently in Kevin's PM branch is merged.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
      69ecefca
  15. 09 1月, 2010 1 次提交
  17. 12 12月, 2009 4 次提交
  19. 09 12月, 2009 1 次提交
  21. 02 12月, 2009 1 次提交
  23. 18 11月, 2009 1 次提交
  25. 21 10月, 2009 1 次提交
    • T
      omap: headers: Move remaining headers from include/mach to include/plat · ce491cf8
      由 Tony Lindgren 提交于 
      Move the remaining headers under plat-omap/include/mach
to plat-omap/include/plat. Also search and replace the
files using these headers to include using the right path.

This was done with:

#!/bin/bash
mach_dir_old="arch/arm/plat-omap/include/mach"
plat_dir_new="arch/arm/plat-omap/include/plat"
headers=$(cd $mach_dir_old && ls *.h)
omap_dirs="arch/arm/*omap*/ \
drivers/video/omap \
sound/soc/omap"
other_files="drivers/leds/leds-ams-delta.c \
drivers/mfd/menelaus.c \
drivers/mfd/twl4030-core.c \
drivers/mtd/nand/ams-delta.c"

for header in $headers; do
	old="#include <mach\/$header"
	new="#include <plat\/$header"
	for dir in $omap_dirs; do
		find $dir -type f -name \*.[chS] | \
			xargs sed -i "s/$old/$new/"
	done
	find drivers/ -type f -name \*omap*.[chS] | \
		xargs sed -i "s/$old/$new/"
	for file in $other_files; do
		sed -i "s/$old/$new/" $file
	done
done

for header in $(ls $mach_dir_old/*.h); do
	git mv $header $plat_dir_new/
done
Signed-off-by: NTony Lindgren <tony@atomide.com>
      ce491cf8
  27. 06 10月, 2009 1 次提交
  29. 04 9月, 2009 1 次提交
  31. 25 7月, 2009 2 次提交
    • P
      OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB · 3c82e229
      由 Paul Walmsley 提交于 
      Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices.  These devices are both interconnect
initiators and targets.  Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:

    Clock usbhost_48m_fck didn't enable in 100000 tries

Two bugs are fixed by this patch.  First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond.  ES1 chips
should not wait for these clocks to enable.  So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.

Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks.  It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1].  Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.

This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].

In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.

Problem reported by Jarkko Nikula <jhnikula@gmail.com>:

    http://marc.info/?l=linux-omap&m=124306184903679&w=2

...

1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
   DSS case).

2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.

3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.htmlSigned-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
      3c82e229
    • J
      OMAP3 SDRC: add support for 2 SDRAM chip selects · 58cda884
      由 Jean Pihet 提交于 
      Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
SDRAM parts connected to the SDRC.

This patch adds the following:
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw
- add the SDRC 2nd CS registers offsets defines
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers

Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).
Signed-off-by: NJean Pihet <jpihet@mvista.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      58cda884
  33. 20 6月, 2009 4 次提交
  35. 29 5月, 2009 1 次提交
  37. 16 5月, 2009 1 次提交
  39. 13 5月, 2009 4 次提交
  41. 20 2月, 2009 1 次提交
    • R
      [ARM] omap: add support for bypassing DPLLs · c0bf3132
      由 Russell King 提交于 
      This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.

For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure.  Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled.  Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately.  Finally, we update the clock's parent, and then
disable the unused clocks.

This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL.  This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c0bf3132
  43. 14 2月, 2009 1 次提交
    • R
      [ARM] omap: arrange for clock recalc methods to return the rate · 8b9dbc16
      由 Russell King 提交于 
      linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce
introduces a way to "dry run" clock changes before they're committed.
However, this involves putting logic to handle this into each and
every recalc function, and unfortunately due to the caching, led to
some bugs.

Solve both of issues by making the recalc methods always return the
clock rate for the clock, which the caller decides what to do with.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      8b9dbc16
  45. 09 2月, 2009 1 次提交