1. 10 10月, 2008 1 次提交
  2. 09 10月, 2008 1 次提交
  3. 25 7月, 2008 1 次提交
    • R
      powerpc/pseries: iommu enablement for CMO · 6490c490
      Robert Jennings 提交于
      To support Cooperative Memory Overcommitment (CMO), we need to check
      for failure from some of the tce hcalls.
      
      These changes for the pseries platform affect the powerpc architecture;
      patches for the other affected platforms are included in this patch.
      
      pSeries platform IOMMU code changes:
       * platform TCE functions must handle H_NOT_ENOUGH_RESOURCES errors and
         return an error.
      
      Architecture IOMMU code changes:
       * Calls to ppc_md.tce_build need to check return values and return
         DMA_MAPPING_ERROR for transient errors.
      
      Architecture changes:
       * struct machdep_calls for tce_build*_pSeriesLP functions need to change
         to indicate failure.
       * all other platforms will need updates to iommu functions to match the new
         calling semantics; they will return 0 on success.  The other platforms
         default configs have been built, but no further testing was performed.
      Signed-off-by: NRobert Jennings <rcj@linux.vnet.ibm.com>
      Acked-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      6490c490
  4. 22 7月, 2008 1 次提交
  5. 19 5月, 2008 1 次提交
  6. 17 4月, 2008 1 次提交
  7. 07 4月, 2008 1 次提交
  8. 06 3月, 2008 3 次提交
  9. 21 2月, 2008 1 次提交
  10. 01 2月, 2008 1 次提交
  11. 31 1月, 2008 1 次提交
  12. 29 1月, 2008 2 次提交
  13. 16 1月, 2008 1 次提交
  14. 03 1月, 2008 2 次提交
  15. 28 12月, 2007 2 次提交
    • O
      [POWERPC] pasemi: Distribute interrupts evenly across cpus · d87bf3be
      Olof Johansson 提交于
      By default the OpenPIC on PWRficient will bias to one core (since that
      will improve changes of the other core being able to stay idle/powered
      down). However, this conflicts with most irq load balancing schemes,
      since setting an interrupt to be delivered to either core doesn't really
      result in the load being shared. It also doesn't work well with the
      soft irq disable feature of PPC, since EE will stay on until the first
      interrupt is taken while soft disabled.
      
      Set the gconf0 config bit that enables even distribution of interrupts
      among the two cores.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      d87bf3be
    • O
      [POWERPC] pasemi: Implement NMI support · f365355e
      Olof Johansson 提交于
      Some PWRficient-based boards have a NMI button that's wired up to a GPIO
      as interrupt source. By configuring the openpic accordingly, these get
      delivered as a machine check with high priority, instead of as an external
      interrupt.
      
      The device tree contains a property "nmi-source" in the openpic node
      for these systems, and it's the (hwirq) source for the input.
      
      Also, for these interrupts, the IACK is read from another register than
      the regular (MCACK instead), but they are EOI'd as usual. So implement
      said function for the mpic driver.
      
      Finally, move a couple of external function defines to include/ instead
      of local under sysdev. Being able to mask/unmask and eoi directly saves
      us from setting up a dummy irq handler that will never be called.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      f365355e
  16. 21 12月, 2007 1 次提交
  17. 20 12月, 2007 1 次提交
    • O
      [POWERPC] pasemi: Implement MSI support · 38958dd9
      Olof Johansson 提交于
      Implement MSI support for PA Semi PWRficient platforms. MSI is done
      through a special range of sources on the openpic controller, and they're
      unfortunately breaking the usual concepts of how sources are programmed:
      
      * The source is calculated as 512 + the value written into the MSI
        register
      * The vector for this source is added to the source and reported
        through IACK
      
      This means that for simplicity, it makes much more sense to just set the
      vector to 0 for the source, since that's really the vector we expect to
      see from IACK.
      
      Also, the affinity/priority registers will affect 16 sources at a
      time. To avoid most (simple) users from being limited by this, allocate
      16 sources per device but use only one. This means that there's a total
      of 32 sources.
      
      If we get usage scenarions that need more sources, the allocator should
      probably be revised to take an alignment argument and size, not just do
      natural alignment.
      
      Finally, since I'm already touching the MPIC names on pasemi, rename
      the base one from the somewhat odd " PAS-OPIC  " to "PASEMI-OPIC".
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      38958dd9
  18. 11 12月, 2007 1 次提交
  19. 06 12月, 2007 1 次提交
  20. 04 12月, 2007 1 次提交
  21. 02 12月, 2007 2 次提交
  22. 30 11月, 2007 2 次提交
  23. 20 11月, 2007 1 次提交
  24. 17 10月, 2007 1 次提交
  25. 11 10月, 2007 2 次提交
  26. 05 10月, 2007 1 次提交
  27. 13 9月, 2007 5 次提交
  28. 25 8月, 2007 1 次提交