[Why + How]
Enable P010 for SDR video applications.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NStylon Wang <stylon.wang@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Change since v1: add brief description
1. Add hdmi frl pcon support to existing asic family.
2. Determine pcon frl capability based on pcon dpcd.
3. pcon frl is taken into consideration into mode validation.

v2: squash in warning fix (Alex)
Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
The previous changes for fixing MPO underflow with multiple
display connected caused a regression where the machine runs
into a hang when doing multiple driver pnp with multiple displays
connected

[HOW]
Reverted offending change
Reviewed-by: NMartin Leung <Martin.Leung@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAngus Wang <angus.wang@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
With RGB MPO enabled, playing a video with multiple displays connected
results in underflow when closing the video window

[HOW]
Reverted the old change to fix this problem, which prevented pipe splits
for multiple display configurations and caused high MCLK speeds during
idle. Added a two step call to dc_update_planes_and_stream, first time
with pipe split disabled and the second time with pipe split enabled,
which fixed the underflow issue
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAngus Wang <angus.wang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
It was found that the system would hang on a dummy pstate when playing
4k60 videos on a 1080p 390Hz monitor.

[HOW]
Properly select the dummy_pstate_latency_ms when firmware assisted
memory clock switching is enabled instead of assuming that the highest
latency would work for every monitor timing.
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NFelipe Clark <felclark@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN301 to DML, where all FPU code
should locate.

Cc: Christian König <christian.koenig@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: NZhan Liu <Zhan.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NQingqing Zhuo <Qingqing.Zhuo@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

fixed16_to_double & fixed16_to_double_to_cpu are not used.
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This change adds a config flag to allow non fullscreen MPO during ODM.
Scaling calculation will still fail configurations where video is only
one one side of the screen.
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

coccinelle patch used:

@@ expression enc1,vpg,afmt; @@
-       if (!enc1 || !vpg || !afmt)
+       if (!enc1 || !vpg || !afmt) {
+               kfree(enc1);
+               kfree(vpg);
+               kfree(afmt);
                return NULL;
+       }

Addresses-Coverity-ID: 1466017: ("Resource leaks")
Reviewed-by: NAurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: NMikita Lipski <mikita.lipski@amd.com>
Signed-off-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Clocks don't get recalculated in 0 stream/0 pipe configs,
blocking S0i3 if dcfclk gets high enough

[HOW]
Create DCN31 copy of DCN30 bandwidth validation func which
doesn't entirely skip validation in 0 pipe scenarios

Override dcfclk to vlevel 0/min value during validation if pipe
count is 0
Reviewed-by: NEric Yang <Eric.Yang2@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NMichael Strauss <michael.strauss@amd.com>
Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
This is a global parameter, not a per pipe parameter and it's useful
for experimenting with the prefetch schedule to be adjustable from
the SOC bb.

[How]
Add a parameter to the SOC bb, default is the existing policy for
all DCN. Fill it in when filling SOC bb parameters.

Revert the policy to use MinDCFClk at the same time since that's not
going to give us P-State in most cases on the spreadsheet.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
DML is initialized again unnecessarily after its done conditionally.
Remove the duplicate initialization

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Drop hardcoded dispclk, dppclk, phyclk

[How]
Read the corresponding values from clock table entries already populated.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
Cc: stable@vger.kernel.org
Signed-off-by: NJerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
The DCN3 SoC parameter num_states was calculated but not saved into the
object.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
Cc: stable@vger.kernel.org
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Cc: stable@vger.kernel.org
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Cc: stable@vger.kernel.org
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
For DCN31 onward, LTTPR is to be enabled and set to Transparent by
VBIOS.  Driver is to assume that VBIOS has done this without needing to
check the VBIOS interop bit.

[HOW]
Add LTTPR enable and interop VBIOS bits into dc->caps, and force-set the
interop bit to true for DCN31+.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
For DCN31 onward, LTTPR is to be enabled and set to Transparent by
VBIOS.  Driver is to assume that VBIOS has done this without needing to
check the VBIOS interop bit.

[HOW]
Add LTTPR enable and interop VBIOS bits into dc->caps, and force-set the
interop bit to true for DCN31+.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Rearranging pipes with multiple displays and multiple planes cannot be
done atomically and requires a much improved sequence to deal with it.

[How]
To workaround such issues, prefer avoid pipe-split policy for
multidisplay scenarios.
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Reviewed-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

/n should be \n
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The
max downscaling limit value for DCN2.x is 250, which means it's
calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167.

[how]
Set maximum downscaling limit to 167 for DCN3.x
Signed-off-by: NNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The
max downscaling limit value for DCN2.x is 250, which means it's
calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167.

[how]
Set maximum downscaling limit to 167 for DCN3.x
Signed-off-by: NNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

[WHY]
to initial ddc structure before we use them to avoid error checking.

[HOW]
add 0 as structure initialization value in DCN resource construct
Signed-off-by: NYu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: NMeenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: NWayne Lin <waynelin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Some hardware revisions do have a max number of lines limitation
not honouring which can cause pstate switch underflow.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SOC needs to be updated to the WM set A values before validation
happens.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Not all ASICs have same plane capabilities so need to split them
out for proper support handling.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAtufa Khan <Atufa.Khan@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable max memory lb config to improve stutter efficiency and
latency hiding. Also increase max number of lb lines to be
used by dml since experiments have shown that there isnt a hard max
beyond what fits in lb.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Ported logic from dcn21 for reading in pipe fusing to dcn30.
Supported configurations are 1 and 6 pipes. Invalid fusing
will revert to 1 pipe being enabled.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Ported logic from dcn21 for reading in pipe fusing to dcn30.
Supported configurations are 1 and 6 pipes. Invalid fusing
will revert to 1 pipe being enabled.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NDillon Varone <dillon.varone@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Hardware team remeasured, need to update timings
to increase latency slightly and avoid intermittent
underflows.

[How]
sr exit latency update.
Signed-off-by: NMartin Leung <martin.leung@amd.com>
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NQingqing Zhuo <Qingqing.Zhuo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some scenarios where we use a UCLK frequency in between dummy p-state table
entries result in a p-state hang, due to the table not having a close
enough match, so the default DPM0 latency is used, which can be too long to
support dummy p-state switching in these scenarios.

[How]
 - old: match if current freq is within +- margin of table entry
 - new: find largest table entry that is lower than current freq + margin
   - lower than DPM0 will still use DPM0
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Initial bounding box values are updated in dcn30_update_bw_bounding_box
 but they use dcn3_0_soc and dcn3_0_ip instead of dcn3_02_soc and
 dcn3_02_ip

[How]
Add dcn302_update_bw_bounding_box and
 dcn302_get_optimal_dcfclk_fclk_for_uclk so it uses
 dcn3_02_soc and dcn3_02_ip.
Use sr_exit_time_us, sr_enter_plus_exit_time_us,
 from dcn30 on dcn302 to fix flicker on eDP.
 Also use dram_clock_change_latency_us from dcn30.
Signed-off-by: NSamson Tam <Samson.Tam@amd.com>
Reviewed-by: NJoshua Aberback <Joshua.Aberback@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
There aren't any ASIC where we use these binaries and they aren't
useful for future use since it's inconvenient to extend and maintain
these structures.

[How]
Drop the support from DM and DC for now.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NRoman Li <Roman.Li@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Acked-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NHersen Wu <hersenxs.wu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[How]
 - use dc interface instead of hwss interface in cursor functions, to keep
dc->idle_optimizations_allowed updated
 - add dc interface to check if idle optimizations might apply to a plane
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The I2C memory blocks should be powered down when they are not in use.
This will reduce power consumption.

[How]
1. Write to I2C_LIGHT_SLEEP_FORCE to put memory in light sleep when
   released
2. Added a debug option to allow this behaviour to be turned off
Signed-off-by: NJacky Liao <ziyu.liao@amd.com>
Acked-by: NBindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Adjust the FP handling to avoid nested calls.

The nested calls cause the warning below
WARNING: CPU: 3 PID: 384 at arch/x86/kernel/fpu/core.c:129 kernel_fpu_begin

Fixes: 582e2ce5 ("drm/amdgpu/display: FP fixes for DCN3.x (v4)")
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When mpo enabled, video comes is 709. Desktop use sRGB.
So color change easily noticeable especially when switch between
mpo/non-mpo.

[How]
Force use sRGB for video TF is sRGB or BT709.
DCN1/DCN2 use predefined type with YUV.
DCN3 use distributed points type with YUV.
Signed-off-by: NJing Zhou <Jing.Zhou@amd.com>
Acked-by: NBindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Due to the freesync power optimization increasing vtotal, the driver
believes that MPO is supported. MPO is turned on. Freesync then
exits, MPO can no longer be supported and immediate flip fails. This
causes corruption on the panel.

[How]
Avoid the freesync optimization when doing validation so in the case
freesync exits, driver can still support the configuration.
Signed-off-by: NIsabel Zhang <isabel.zhang@amd.com>
Acked-by: NBindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add proper FP_START/END handling and adjust Makefiles per
previous asics.

v2: fix up harder.
v3: fix clkmgr Makefile for dcn30
v4: fix old gcc handling is only required for x86
Build-tested-by: NNathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com> (v1)
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> (v1)
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We need this to pass dp compliance.
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NChris Park <Chris.Park@amd.com>
Reviewed-by: NNikola Cornij <nikola.cornij@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>